I2C Bus Monitor Register IBMR 0x00000003 00000000 00000000 00000000 00000011 IBMR_SDAS 1 SDA Status IBMR_SCLS 1 SDA Status I2C Data Buffer Register IDBR 0x00000008 00000000 00000000 00000000 00001000 IDBR_IDB 8 I2C Data Buffer I2C Control Register ICR 0x000017e0 00000000 00000000 00010111 11100000 ICR_START 0 start bit ICR_STOP 0 stop bit ICR_ACKNAK 0 send ACK(0) or NAK(1) ICR_TB 0 transfer byte bit ICR_MA 0 master abort ICR_SCLE 1 master clock enable ICR_IUE 1 unit enable ICR_GCD 1 general call disable ICR_ITEIE 1 enable tx interrupts ICR_IRFIE 1 enable rx interrupts ICR_BEIE 1 enable bus error ints ICR_SSDIE 0 slave STOP detected int enable ICR_ALDIE 1 enable arbitration interrupt ICR_SADIE 0 slave address detected int enable ICR_UR 0 unit reset ICR_FM 0 fast mode I2C Status Register ISR 0x00000000 00000000 00000000 00000000 00000000 ISR_RWM 0 read/write mode ISR_ACKNAK 0 ack/nak status ISR_UB 0 unit busy ISR_IBB 0 bus busy ISR_SSD 0 slave stop detected ISR_ALD 0 arbitration loss detected ISR_ITE 0 tx buffer empty ISR_IRF 0 rx buffer full ISR_GCAD 0 general call address detected ISR_SAD 0 slave address detected ISR_BED 0 bus error no ACK/NAK I2C Slave Address Register ISAR 0x00000001 00000000 00000000 00000000 00000001 ISAR_SA 1 I2C Slave Address USB Port 2 Output Control Register UP2OCR 0x000200b0 00000000 00000010 00000000 10110000 UP2OCR_CPVEN 0 Charge Pump Vbus Enable UP2OCR_CPVPE 0 Charge Pump Vbus Pulse Enable UP2OCR_DPPDE 0 Host Port 2 Transceiver D+ Pull Down Enable UP2OCR_DMPDE 0 Host Port 2 Transceiver D- Pull Down Enable UP2OCR_DPPUE 1 Host Port 2 Transceiver D+ Pull Up Enable UP2OCR_DMPUE 1 Host Port 2 Transceiver D- Pull Up Enable UP2OCR_DPPUBE 0 Host Port 2 Transceiver D+ Pull Up Bypass Enable UP2OCR_DMPUBE 1 Host Port 2 Transceiver D- Pull Up Bypass Enable UP2OCR_EXSP 0 External Transceiver Speed Control UP2OCR_EXSUS 0 External Transceiver Suspend Enable UP2OCR_IDON 0 OTG ID Read Enable UP2OCR_HXS 0 USB Port 2 Tranceiver Output Select UP2OCR_HXOE 1 USB Port 2 Tranceiver OE UP2OCR_SEOS 0 USB Port 2 Single-Ended Output Select HWUART Modem Control Register HW_MCR 0x00000100 00000000 00000000 00000001 00000000 HWUART Modem Status Register HW_MSR 0x00000003 00000000 00000000 00000000 00000011 Power Manager Control Register (3-23) PMCR 0x00000000 00000000 00000000 00000000 00000000 PMCR_IDAE 0 PM imprecise data abort abort signal Power Manager Sleep Status Register (3-29) PSSR 0x00000000 00000000 00000000 00000000 00000000 PSSR_SSS 0 PM chip was in sleep by setting sleep mode bit PSSR_BFS 0 PM nBATT_FAULT has been asserted PSSR_VFS 0 PM nVDD_FAULT was asserted while in Run or Idle PSSR_PH 0 PM GPIO pins are held in their sleep state PSSR_RDH 0 PM receivers of all input GPIO are disabled Power Manager Scratch Pad Register (3-30) PSPR 0x00000000 00000000 00000000 00000000 00000000 Power Manager Wake-Up Enable Register (3-25) PWER 0x00000002 00000000 00000000 00000000 00000010 PWER_WE0 0 PM wake up due to GPIO 0 edge detect enabled PWER_WE1 1 PM wake up due to GPIO 1 edge detect enabled PWER_WE2 0 PM wake up due to GPIO 2 edge detect enabled PWER_WE3 0 PM wake up due to GPIO 3 edge detect enabled PWER_WE4 0 PM wake up due to GPIO 4 edge detect enabled PWER_WE5 0 PM wake up due to GPIO 5 edge detect enabled PWER_WE6 0 PM wake up due to GPIO 6 edge detect enabled PWER_WE7 0 PM wake up due to GPIO 7 edge detect enabled PWER_WE8 0 PM wake up due to GPIO 8 edge detect enabled PWER_WE9 0 PM wake up due to GPIO 9 edge detect enabled PWER_WE10 0 PM wake up due to GPIO10 edge detect enabled PWER_WE11 0 PM wake up due to GPIO11 edge detect enabled PWER_WE12 0 PM wake up due to GPIO12 edge detect enabled PWER_WE13 0 PM wake up due to GPIO13 edge detect enabled PWER_WE14 0 PM wake up due to GPIO14 edge detect enabled PWER_WE15 0 PM wake up due to GPIO15 edge detect enabled PWER_WERTC 0 PM wake up due to RTC alarm enabled Power Manager Rising Edge Detect Enable Register (3-26) PRER 0x00000003 00000000 00000000 00000000 00000011 PRER_RE0 1 PM wake up due to GPIO 0 rising edge detect enabled PRER_RE1 1 PM wake up due to GPIO 1 rising edge detect enabled PRER_RE2 0 PM wake up due to GPIO 2 rising edge detect enabled PRER_RE3 0 PM wake up due to GPIO 3 rising edge detect enabled PRER_RE4 0 PM wake up due to GPIO 4 rising edge detect enabled PRER_RE5 0 PM wake up due to GPIO 5 rising edge detect enabled PRER_RE6 0 PM wake up due to GPIO 6 rising edge detect enabled PRER_RE7 0 PM wake up due to GPIO 7 rising edge detect enabled PRER_RE8 0 PM wake up due to GPIO 8 rising edge detect enabled PRER_RE9 0 PM wake up due to GPIO 9 rising edge detect enabled PRER_RE10 0 PM wake up due to GPIO10 rising edge detect enabled PRER_RE11 0 PM wake up due to GPIO11 rising edge detect enabled PRER_RE12 0 PM wake up due to GPIO12 rising edge detect enabled PRER_RE13 0 PM wake up due to GPIO13 rising edge detect enabled PRER_RE14 0 PM wake up due to GPIO14 rising edge detect enabled PRER_RE15 0 PM wake up due to GPIO15 rising edge detect enabled Power Manager Falling Detect Enable Register (3-27) PFER 0x00000003 00000000 00000000 00000000 00000011 PFER_FE0 1 PM wake up due to GPIO 0 falling edge detect enabled PFER_FE1 1 PM wake up due to GPIO 1 falling edge detect enabled PFER_FE2 0 PM wake up due to GPIO 2 falling edge detect enabled PFER_FE3 0 PM wake up due to GPIO 3 falling edge detect enabled PFER_FE4 0 PM wake up due to GPIO 4 falling edge detect enabled PFER_FE5 0 PM wake up due to GPIO 5 falling edge detect enabled PFER_FE6 0 PM wake up due to GPIO 6 falling edge detect enabled PFER_FE7 0 PM wake up due to GPIO 7 falling edge detect enabled PFER_FE8 0 PM wake up due to GPIO 8 falling edge detect enabled PFER_FE9 0 PM wake up due to GPIO 9 falling edge detect enabled PFER_FE10 0 PM wake up due to GPIO10 falling edge detect enabled PFER_FE11 0 PM wake up due to GPIO11 falling edge detect enabled PFER_FE12 0 PM wake up due to GPIO12 falling edge detect enabled PFER_FE13 0 PM wake up due to GPIO13 falling edge detect enabled PFER_FE14 0 PM wake up due to GPIO14 falling edge detect enabled PFER_FE15 0 PM wake up due to GPIO15 falling edge detect enabled Power Manager Edge Detect Status Register (3-28) PEDR 0x00000000 00000000 00000000 00000000 00000000 PEDR_ED0 0 PM wake up due to edge on GPIO 0 detected PEDR_ED1 0 PM wake up due to edge on GPIO 1 detected PEDR_ED2 0 PM wake up due to edge on GPIO 2 detected PEDR_ED3 0 PM wake up due to edge on GPIO 3 detected PEDR_ED4 0 PM wake up due to edge on GPIO 4 detected PEDR_ED5 0 PM wake up due to edge on GPIO 5 detected PEDR_ED6 0 PM wake up due to edge on GPIO 6 detected PEDR_ED7 0 PM wake up due to edge on GPIO 7 detected PEDR_ED8 0 PM wake up due to edge on GPIO 8 detected PEDR_ED9 0 PM wake up due to edge on GPIO 9 detected PEDR_ED10 0 PM wake up due to edge on GPIO10 detected PEDR_ED11 0 PM wake up due to edge on GPIO11 detected PEDR_ED12 0 PM wake up due to edge on GPIO12 detected PEDR_ED13 0 PM wake up due to edge on GPIO13 detected PEDR_ED14 0 PM wake up due to edge on GPIO14 detected PEDR_ED15 0 PM wake up due to edge on GPIO15 detected Power Manager General Configuration Register (3-24) PCFR 0x00000020 00000000 00000000 00000000 00100000 PCFR_OPDE 0 PM stop 3.6864 MHz oscillator during sleep PCFR_FP 0 PM PCMCIA signals float during sleep PCFR_FS 0 PM static chip select signals float during sleep Power Manager GPIO Sleep State Register 0 (3-32) PGSR0 0x00000000 00000000 00000000 00000000 00000000 PGSR_SS0 0 PM GPIO pin 0 is driven to 1 during sleep PGSR_SS1 0 PM GPIO pin 1 is driven to 1 during sleep PGSR_SS2 0 PM GPIO pin 2 is driven to 1 during sleep PGSR_SS3 0 PM GPIO pin 3 is driven to 1 during sleep PGSR_SS4 0 PM GPIO pin 4 is driven to 1 during sleep PGSR_SS5 0 PM GPIO pin 5 is driven to 1 during sleep PGSR_SS6 0 PM GPIO pin 6 is driven to 1 during sleep PGSR_SS7 0 PM GPIO pin 7 is driven to 1 during sleep PGSR_SS8 0 PM GPIO pin 8 is driven to 1 during sleep PGSR_SS9 0 PM GPIO pin 9 is driven to 1 during sleep PGSR_SS10 0 PM GPIO pin 10 is driven to 1 during sleep PGSR_SS11 0 PM GPIO pin 11 is driven to 1 during sleep PGSR_SS12 0 PM GPIO pin 12 is driven to 1 during sleep PGSR_SS13 0 PM GPIO pin 13 is driven to 1 during sleep PGSR_SS14 0 PM GPIO pin 14 is driven to 1 during sleep PGSR_SS15 0 PM GPIO pin 15 is driven to 1 during sleep PGSR_SS16 0 PM GPIO pin 16 is driven to 1 during sleep PGSR_SS17 0 PM GPIO pin 17 is driven to 1 during sleep PGSR_SS18 0 PM GPIO pin 18 is driven to 1 during sleep PGSR_SS19 0 PM GPIO pin 19 is driven to 1 during sleep PGSR_SS20 0 PM GPIO pin 20 is driven to 1 during sleep PGSR_SS21 0 PM GPIO pin 21 is driven to 1 during sleep PGSR_SS22 0 PM GPIO pin 22 is driven to 1 during sleep PGSR_SS23 0 PM GPIO pin 23 is driven to 1 during sleep PGSR_SS24 0 PM GPIO pin 24 is driven to 1 during sleep PGSR_SS25 0 PM GPIO pin 25 is driven to 1 during sleep PGSR_SS26 0 PM GPIO pin 26 is driven to 1 during sleep PGSR_SS27 0 PM GPIO pin 27 is driven to 1 during sleep PGSR_SS28 0 PM GPIO pin 28 is driven to 1 during sleep PGSR_SS29 0 PM GPIO pin 29 is driven to 1 during sleep PGSR_SS30 0 PM GPIO pin 30 is driven to 1 during sleep PGSR_SS31 0 PM GPIO pin 31 is driven to 1 during sleep Power Manager GPIO Sleep State Register 1 (3-32) PGSR1 0x00008208 00000000 00000000 10000010 00001000 PGSR_SS32 0 PM GPIO pin 32 is driven to 1 during sleep PGSR_SS33 0 PM GPIO pin 33 is driven to 1 during sleep PGSR_SS34 0 PM GPIO pin 34 is driven to 1 during sleep PGSR_SS35 1 PM GPIO pin 35 is driven to 1 during sleep PGSR_SS36 0 PM GPIO pin 36 is driven to 1 during sleep PGSR_SS37 0 PM GPIO pin 37 is driven to 1 during sleep PGSR_SS38 0 PM GPIO pin 38 is driven to 1 during sleep PGSR_SS39 0 PM GPIO pin 39 is driven to 1 during sleep PGSR_SS40 0 PM GPIO pin 40 is driven to 1 during sleep PGSR_SS41 1 PM GPIO pin 41 is driven to 1 during sleep PGSR_SS42 0 PM GPIO pin 42 is driven to 1 during sleep PGSR_SS43 0 PM GPIO pin 43 is driven to 1 during sleep PGSR_SS44 0 PM GPIO pin 44 is driven to 1 during sleep PGSR_SS45 0 PM GPIO pin 45 is driven to 1 during sleep PGSR_SS46 0 PM GPIO pin 46 is driven to 1 during sleep PGSR_SS47 1 PM GPIO pin 47 is driven to 1 during sleep PGSR_SS48 0 PM GPIO pin 48 is driven to 1 during sleep PGSR_SS49 0 PM GPIO pin 49 is driven to 1 during sleep PGSR_SS50 0 PM GPIO pin 50 is driven to 1 during sleep PGSR_SS51 0 PM GPIO pin 51 is driven to 1 during sleep PGSR_SS52 0 PM GPIO pin 52 is driven to 1 during sleep PGSR_SS53 0 PM GPIO pin 53 is driven to 1 during sleep PGSR_SS54 0 PM GPIO pin 54 is driven to 1 during sleep PGSR_SS55 0 PM GPIO pin 55 is driven to 1 during sleep PGSR_SS56 0 PM GPIO pin 56 is driven to 1 during sleep PGSR_SS57 0 PM GPIO pin 57 is driven to 1 during sleep PGSR_SS58 0 PM GPIO pin 58 is driven to 1 during sleep PGSR_SS59 0 PM GPIO pin 59 is driven to 1 during sleep PGSR_SS60 0 PM GPIO pin 60 is driven to 1 during sleep PGSR_SS61 0 PM GPIO pin 61 is driven to 1 during sleep PGSR_SS62 0 PM GPIO pin 62 is driven to 1 during sleep PGSR_SS63 0 PM GPIO pin 63 is driven to 1 during sleep Power Manager GPIO Sleep State Register 2 (3-33) PGSR2 0x00000000 00000000 00000000 00000000 00000000 PGSR_SS64 0 PM GPIO pin 64 is driven to 1 during sleep PGSR_SS65 0 PM GPIO pin 65 is driven to 1 during sleep PGSR_SS66 0 PM GPIO pin 66 is driven to 1 during sleep PGSR_SS67 0 PM GPIO pin 67 is driven to 1 during sleep PGSR_SS68 0 PM GPIO pin 68 is driven to 1 during sleep PGSR_SS69 0 PM GPIO pin 69 is driven to 1 during sleep PGSR_SS70 0 PM GPIO pin 70 is driven to 1 during sleep PGSR_SS71 0 PM GPIO pin 71 is driven to 1 during sleep PGSR_SS72 0 PM GPIO pin 72 is driven to 1 during sleep PGSR_SS73 0 PM GPIO pin 73 is driven to 1 during sleep PGSR_SS74 0 PM GPIO pin 74 is driven to 1 during sleep PGSR_SS75 0 PM GPIO pin 75 is driven to 1 during sleep PGSR_SS76 0 PM GPIO pin 76 is driven to 1 during sleep PGSR_SS77 0 PM GPIO pin 77 is driven to 1 during sleep PGSR_SS78 0 PM GPIO pin 78 is driven to 1 during sleep PGSR_SS79 0 PM GPIO pin 79 is driven to 1 during sleep PGSR_SS80 0 PM GPIO pin 80 is driven to 1 during sleep Power Manager Reset Controller Status Register (3-34) RCSR 0x00000000 00000000 00000000 00000000 00000000 RCSR_HWR 0 PM hardware reset occurred RCSR_WDR 0 PM watchdog reset occurred RCSR_SMR 0 PM sleep mode occurred RCSR_GFR 0 PM GPIO reset occurred Power Manager Fast Sleep Wakeup Register (3-31) PMFW 0xcc000000 11001100 00000000 00000000 00000000 PMFW_FWAKE 0 Fast Wakeup Enable Power Manager Keyboard Wake-Up Enable Register (3-28 PXA270) PKWR 0x00000000 00000000 00000000 00000000 00000000 PKWR_WE13 0 PM GPIO pin 13 wake up enabled, high true PKWR_WE16 0 PM GPIO pin 16 wake up enabled, high true PKWR_WE17 0 PM GPIO pin 17 wake up enabled, high true PKWR_WE34 0 PM GPIO pin 34 wake up enabled, high true PKWR_WE36 0 PM GPIO pin 36 wake up enabled, high true PKWR_WE37 0 PM GPIO pin 37 wake up enabled, high true PKWR_WE38 0 PM GPIO pin 38 wake up enabled, high true PKWR_WE39 0 PM GPIO pin 39 wake up enabled, high true PKWR_WE90 0 PM GPIO pin 90 wake up enabled, high true PKWR_WE91 0 PM GPIO pin 91 wake up enabled, high true PKWR_WE93 0 PM GPIO pin 93 wake up enabled, high true PKWR_WE94 0 PM GPIO pin 94 wake up enabled, high true PKWR_WE95 0 PM GPIO pin 95 wake up enabled, high true PKWR_WE96 0 PM GPIO pin 96 wake up enabled, high true PKWR_WE97 0 PM GPIO pin 97 wake up enabled, high true PKWR_WE98 0 PM GPIO pin 98 wake up enabled, high true PKWR_WE99 0 PM GPIO pin 99 wake up enabled, high true PKWR_WE100 0 PM GPIO pin 100 wake up enabled, high true PKWR_WE101 0 PM GPIO pin 101 wake up enabled, high true PKWR_WE102 0 PM GPIO pin 102 wake up enabled, high true Core Clock Configuration Register (3-35) CCCR 0x02000190 00000010 00000000 00000001 10010000 CCCR_L 10 CM crystal freq to memory freq multiplier CCCR_M 0 CM memory freq to run mode freq multiplier CCCR_N 3 CM run mode freq to turbo freq multiplier Clock Enable Register (3-36) CKEN 0x00d95e2b 00000000 11011001 01011110 00101011 CKEN_0 1 CM PWM0 clock enabled CKEN_1 1 CM PWM1 clock enabled CKEN_2 0 CM AC97 clock enabled CKEN_3 1 CM SSP clock enabled CKEN_4 0 CM SSP3 clock enable CKEN_5 1 CM STUART clock enabled CKEN_6 0 CM FFUART clock enabled CKEN_7 0 CM BTUART clock enabled CKEN_8 0 CM I2S clock enabled CKEN_9 1 OS Timer clock enable CKEN_10 1 USB Host clock enable CKEN_11 1 CM USB clock enabled CKEN_12 1 CM MMC clock enabled CKEN_13 0 CM FIPC clock enabled CKEN_14 1 CM I2C clock enabled CKEN_15 0 Power Manager I2C clock enable CKEN_16 1 CM LCD clock enabled CKEN_17 0 MSL clock enable CKEN_18 0 USIM clock enable CKEN_19 1 Keypad clock enable CKEN_20 1 Internal Memory clock enable CKEN_21 0 Memeory Stick clock enable CKEN_22 1 Memory Controller clock enable CKEN_23 1 SSP1 clock enable CKEN_24 0 Quick Capture clock enable Oscillator Configuration Register (3-38) OSCC 0x00000000 00000000 00000000 00000000 00000000 OSCC_OOK 0 CM 32.768 kHz oscillator enabled and stabilized OSCC_OON 0 CM 32.768 kHz oscillator enabled GPIO Pin Level Register 0 (4-7) GPLR0 0xa5884dff 10100101 10001000 01001101 11111111 GPLR0_0 1 GPIO 0 level GPLR0_1 1 GPIO 1 level GPLR0_2 1 GPIO 2 level GPLR0_3 1 GPIO 3 level GPLR0_4 1 GPIO 4 level GPLR0_5 1 GPIO 5 level GPLR0_6 1 GPIO 6 level GPLR0_7 1 GPIO 7 level GPLR0_8 1 GPIO 8 level GPLR0_9 0 GPIO 9 level GPLR0_10 1 GPIO 10 level GPLR0_11 1 GPIO 11 level GPLR0_12 0 GPIO 12 level GPLR0_13 0 GPIO 13 level GPLR0_14 1 GPIO 14 level GPLR0_15 0 GPIO 15 level GPLR0_16 0 GPIO 16 level GPLR0_17 0 GPIO 17 level GPLR0_18 0 GPIO 18 level GPLR0_19 1 GPIO 19 level GPLR0_20 0 GPIO 20 level GPLR0_21 0 GPIO 21 level GPLR0_22 0 GPIO 22 level GPLR0_23 1 GPIO 23 level GPLR0_24 1 GPIO 24 level GPLR0_25 0 GPIO 25 level GPLR0_26 1 GPIO 26 level GPLR0_27 0 GPIO 27 level GPLR0_28 0 GPIO 28 level GPLR0_29 1 GPIO 29 level GPLR0_30 0 GPIO 30 level GPLR0_31 1 GPIO 31 level GPIO Level Register 1 (4-8) GPLR1 0x0043ca38 00000000 01000011 11001010 00111000 GPLR1_32 0 GPIO 32 level GPLR1_33 0 GPIO 33 level GPLR1_34 0 GPIO 34 level GPLR1_35 1 GPIO 35 level GPLR1_36 1 GPIO 36 level GPLR1_37 1 GPIO 37 level GPLR1_38 0 GPIO 38 level GPLR1_39 0 GPIO 39 level GPLR1_40 0 GPIO 40 level GPLR1_41 1 GPIO 41 level GPLR1_42 0 GPIO 42 level GPLR1_43 1 GPIO 43 level GPLR1_44 0 GPIO 44 level GPLR1_45 0 GPIO 45 level GPLR1_46 1 GPIO 46 level GPLR1_47 1 GPIO 47 level GPLR1_48 1 GPIO 48 level GPLR1_49 1 GPIO 49 level GPLR1_50 0 GPIO 50 level GPLR1_51 0 GPIO 51 level GPLR1_52 0 GPIO 52 level GPLR1_53 0 GPIO 53 level GPLR1_54 1 GPIO 54 level GPLR1_55 0 GPIO 55 level GPLR1_56 0 GPIO 56 level GPLR1_57 0 GPIO 57 level GPLR1_58 0 GPIO 58 level GPLR1_59 0 GPIO 59 level GPLR1_60 0 GPIO 60 level GPLR1_61 0 GPIO 61 level GPLR1_62 0 GPIO 62 level GPLR1_63 0 GPIO 63 level GPIO Level Register 2 (4-8) GPLR2 0x1b240c00 00011011 00100100 00001100 00000000 GPLR2_64 0 GPIO 64 level GPLR2_65 0 GPIO 65 level GPLR2_66 0 GPIO 66 level GPLR2_67 0 GPIO 67 level GPLR2_68 0 GPIO 68 level GPLR2_69 0 GPIO 69 level GPLR2_70 0 GPIO 70 level GPLR2_71 0 GPIO 71 level GPLR2_72 0 GPIO 72 level GPLR2_73 0 GPIO 73 level GPLR2_74 1 GPIO 74 level GPLR2_75 1 GPIO 75 level GPLR2_76 0 GPIO 76 level GPLR2_77 0 GPIO 77 level GPLR2_78 0 GPIO 78 level GPLR2_79 0 GPIO 79 level GPLR2_80 0 GPIO 80 level GPLR2_81 0 GPIO 81 level GPLR2_82 1 GPIO 82 level GPLR2_83 0 GPIO 83 level GPLR2_84 0 GPIO 84 level GPLR2_85 1 GPIO 85 level GPLR2_86 0 GPIO 86 level GPLR2_87 0 GPIO 87 level GPLR2_88 1 GPIO 88 level GPLR2_89 1 GPIO 89 level GPLR2_90 0 GPIO 90 level GPLR2_91 1 GPIO 91 level GPLR2_92 1 GPIO 92 level GPLR2_93 0 GPIO 93 level GPLR2_94 0 GPIO 94 level GPLR2_95 0 GPIO 95 level GPIO Set Register 3 (96-120) GPLR3 0x01e9ff85 00000001 11101001 11111111 10000101 GPLR3_96 1 GPIO 96 level GPLR3_97 0 GPIO 97 level GPLR3_98 1 GPIO 98 level GPLR3_99 0 GPIO 99 level GPLR3_100 0 GPIO 100 level GPLR3_101 0 GPIO 101 level GPLR3_102 0 GPIO 102 level GPLR3_103 1 GPIO 103 level GPLR3_104 1 GPIO 104 level GPLR3_105 1 GPIO 105 level GPLR3_106 1 GPIO 106 level GPLR3_107 1 GPIO 107 level GPLR3_108 1 GPIO 108 level GPLR3_109 1 GPIO 109 level GPLR3_110 1 GPIO 110 level GPLR3_111 1 GPIO 111 level GPLR3_112 1 GPIO 112 level GPLR3_113 0 GPIO 113 level GPLR3_114 0 GPIO 114 level GPLR3_115 1 GPIO 115 level GPLR3_116 0 GPIO 116 level GPLR3_117 1 GPIO 117 level GPLR3_118 1 GPIO 118 level GPLR3_119 1 GPIO 119 level GPLR3_120 1 GPIO 120 level GPIO Direction Register 0 (4-9) GPDR0 0xdbbcfe00 11011011 10111100 11111110 00000000 GPDR0_0 0 GPIO 0 i/o direction (1=output) GPDR0_1 0 GPIO 1 i/o direction (1=output) GPDR0_2 0 GPIO 2 i/o direction (1=output) GPDR0_3 0 GPIO 3 i/o direction (1=output) GPDR0_4 0 GPIO 4 i/o direction (1=output) GPDR0_5 0 GPIO 5 i/o direction (1=output) GPDR0_6 0 GPIO 6 i/o direction (1=output) GPDR0_7 0 GPIO 7 i/o direction (1=output) GPDR0_8 0 GPIO 8 i/o direction (1=output) GPDR0_9 1 GPIO 9 i/o direction (1=output) GPDR0_10 1 GPIO 10 i/o direction (1=output) GPDR0_11 1 GPIO 11 i/o direction (1=output) GPDR0_12 1 GPIO 12 i/o direction (1=output) GPDR0_13 1 GPIO 13 i/o direction (1=output) GPDR0_14 1 GPIO 14 i/o direction (1=output) GPDR0_15 1 GPIO 15 i/o direction (1=output) GPDR0_16 0 GPIO 16 i/o direction (1=output) GPDR0_17 0 GPIO 17 i/o direction (1=output) GPDR0_18 1 GPIO 18 i/o direction (1=output) GPDR0_19 1 GPIO 19 i/o direction (1=output) GPDR0_20 1 GPIO 20 i/o direction (1=output) GPDR0_21 1 GPIO 21 i/o direction (1=output) GPDR0_22 0 GPIO 22 i/o direction (1=output) GPDR0_23 1 GPIO 23 i/o direction (1=output) GPDR0_24 1 GPIO 24 i/o direction (1=output) GPDR0_25 1 GPIO 25 i/o direction (1=output) GPDR0_26 0 GPIO 26 i/o direction (1=output) GPDR0_27 1 GPIO 27 i/o direction (1=output) GPDR0_28 1 GPIO 28 i/o direction (1=output) GPDR0_29 0 GPIO 29 i/o direction (1=output) GPDR0_30 1 GPIO 30 i/o direction (1=output) GPDR0_31 1 GPIO 31 i/o direction (1=output) GPIO Direction Register 1 (4-9) GPDR1 0xffffba8b 11111111 11111111 10111010 10001011 GPDR1_32 1 GPIO 32 i/o direction (1=output) GPDR1_33 1 GPIO 33 i/o direction (1=output) GPDR1_34 0 GPIO 34 i/o direction (1=output) GPDR1_35 1 GPIO 35 i/o direction (1=output) GPDR1_36 0 GPIO 36 i/o direction (1=output) GPDR1_37 0 GPIO 37 i/o direction (1=output) GPDR1_38 0 GPIO 38 i/o direction (1=output) GPDR1_39 1 GPIO 39 i/o direction (1=output) GPDR1_40 0 GPIO 40 i/o direction (1=output) GPDR1_41 1 GPIO 41 i/o direction (1=output) GPDR1_42 0 GPIO 42 i/o direction (1=output) GPDR1_43 1 GPIO 43 i/o direction (1=output) GPDR1_44 1 GPIO 44 i/o direction (1=output) GPDR1_45 1 GPIO 45 i/o direction (1=output) GPDR1_46 0 GPIO 46 i/o direction (1=output) GPDR1_47 1 GPIO 47 i/o direction (1=output) GPDR1_48 1 GPIO 48 i/o direction (1=output) GPDR1_49 1 GPIO 49 i/o direction (1=output) GPDR1_50 1 GPIO 50 i/o direction (1=output) GPDR1_51 1 GPIO 51 i/o direction (1=output) GPDR1_52 1 GPIO 52 i/o direction (1=output) GPDR1_53 1 GPIO 53 i/o direction (1=output) GPDR1_54 1 GPIO 54 i/o direction (1=output) GPDR1_55 1 GPIO 55 i/o direction (1=output) GPDR1_56 1 GPIO 56 i/o direction (1=output) GPDR1_57 1 GPIO 57 i/o direction (1=output) GPDR1_58 1 GPIO 58 i/o direction (1=output) GPDR1_59 1 GPIO 59 i/o direction (1=output) GPDR1_60 1 GPIO 60 i/o direction (1=output) GPDR1_61 1 GPIO 61 i/o direction (1=output) GPDR1_62 1 GPIO 62 i/o direction (1=output) GPDR1_63 1 GPIO 63 i/o direction (1=output) GPIO Direction Register 2 (4-9) GPDR2 0xeffbffff 11101111 11111011 11111111 11111111 GPDR2_64 1 GPIO 64 i/o direction (1=output) GPDR2_65 1 GPIO 65 i/o direction (1=output) GPDR2_66 1 GPIO 66 i/o direction (1=output) GPDR2_67 1 GPIO 67 i/o direction (1=output) GPDR2_68 1 GPIO 68 i/o direction (1=output) GPDR2_69 1 GPIO 69 i/o direction (1=output) GPDR2_70 1 GPIO 70 i/o direction (1=output) GPDR2_71 1 GPIO 71 i/o direction (1=output) GPDR2_72 1 GPIO 72 i/o direction (1=output) GPDR2_73 1 GPIO 73 i/o direction (1=output) GPDR2_74 1 GPIO 74 i/o direction (1=output) GPDR2_75 1 GPIO 75 i/o direction (1=output) GPDR2_76 1 GPIO 76 i/o direction (1=output) GPDR2_77 1 GPIO 77 i/o direction (1=output) GPDR2_78 1 GPIO 78 i/o direction (1=output) GPDR2_79 1 GPIO 79 i/o direction (1=output) GPDR2_80 1 GPIO 80 i/o direction (1=output) GPDR2_81 1 GPIO 81 i/o direction (1=output) GPDR2_82 0 GPIO 82 i/o direction (1=output) GPDR2_83 1 GPIO 83 i/o direction (1=output) GPDR2_84 1 GPIO 84 i/o direction (1=output) GPDR2_85 1 GPIO 85 i/o direction (1=output) GPDR2_86 1 GPIO 86 i/o direction (1=output) GPDR2_87 1 GPIO 87 i/o direction (1=output) GPDR2_88 1 GPIO 88 i/o direction (1=output) GPDR2_89 1 GPIO 89 i/o direction (1=output) GPDR2_90 1 GPIO 90 i/o direction (1=output) GPDR2_91 1 GPIO 91 i/o direction (1=output) GPDR2_92 0 GPIO 92 i/o direction (1=output) GPDR2_93 1 GPIO 93 i/o direction (1=output) GPDR2_94 1 GPIO 94 i/o direction (1=output) GPDR2_95 1 GPIO 95 i/o direction (1=output) GPIO Set Register 3 (96-120) GPDR3 0x001e1f8a 00000000 00011110 00011111 10001010 GPDR3_96 0 GPIO 96 i/o direction (1=output) GPDR3_97 1 GPIO 97 i/o direction (1=output) GPDR3_98 0 GPIO 98 i/o direction (1=output) GPDR3_99 1 GPIO 99 i/o direction (1=output) GPDR3_100 0 GPIO 100 i/o direction (1=output) GPDR3_101 0 GPIO 101 i/o direction (1=output) GPDR3_102 0 GPIO 102 i/o direction (1=output) GPDR3_103 1 GPIO 103 i/o direction (1=output) GPDR3_104 1 GPIO 104 i/o direction (1=output) GPDR3_105 1 GPIO 105 i/o direction (1=output) GPDR3_106 1 GPIO 106 i/o direction (1=output) GPDR3_107 1 GPIO 107 i/o direction (1=output) GPDR3_108 1 GPIO 108 i/o direction (1=output) GPDR3_109 0 GPIO 109 i/o direction (1=output) GPDR3_110 0 GPIO 110 i/o direction (1=output) GPDR3_111 0 GPIO 111 i/o direction (1=output) GPDR3_112 0 GPIO 112 i/o direction (1=output) GPDR3_113 1 GPIO 113 i/o direction (1=output) GPDR3_114 1 GPIO 114 i/o direction (1=output) GPDR3_115 1 GPIO 115 i/o direction (1=output) GPDR3_116 1 GPIO 116 i/o direction (1=output) GPDR3_117 0 GPIO 117 i/o direction (1=output) GPDR3_118 0 GPIO 118 i/o direction (1=output) GPDR3_119 0 GPIO 119 i/o direction (1=output) GPDR3_120 0 GPIO 120 i/o direction (1=output) GPIO Set Register 0 (4-10) GPSR0 0x00000000 00000000 00000000 00000000 00000000 GPSR0_0 0 GPIO 0 set GPSR0_1 0 GPIO 1 set GPSR0_2 0 GPIO 2 set GPSR0_3 0 GPIO 3 set GPSR0_4 0 GPIO 4 set GPSR0_5 0 GPIO 5 set GPSR0_6 0 GPIO 6 set GPSR0_7 0 GPIO 7 set GPSR0_8 0 GPIO 8 set GPSR0_9 0 GPIO 9 set GPSR0_10 0 GPIO 10 set GPSR0_11 0 GPIO 11 set GPSR0_12 0 GPIO 12 set GPSR0_13 0 GPIO 13 set GPSR0_14 0 GPIO 14 set GPSR0_15 0 GPIO 15 set GPSR0_16 0 GPIO 16 set GPSR0_17 0 GPIO 17 set GPSR0_18 0 GPIO 18 set GPSR0_19 0 GPIO 19 set GPSR0_20 0 GPIO 20 set GPSR0_21 0 GPIO 21 set GPSR0_22 0 GPIO 22 set GPSR0_23 0 GPIO 23 set GPSR0_24 0 GPIO 24 set GPSR0_25 0 GPIO 25 set GPSR0_26 0 GPIO 26 set GPSR0_27 0 GPIO 27 set GPSR0_28 0 GPIO 28 set GPSR0_29 0 GPIO 29 set GPSR0_30 0 GPIO 30 set GPSR0_31 0 GPIO 31 set GPIO Set Register 1 (4-10) GPSR1 0x00000000 00000000 00000000 00000000 00000000 GPSR1_32 0 GPIO 32 set GPSR1_33 0 GPIO 33 set GPSR1_34 0 GPIO 34 set GPSR1_35 0 GPIO 35 set GPSR1_36 0 GPIO 36 set GPSR1_37 0 GPIO 37 set GPSR1_38 0 GPIO 38 set GPSR1_39 0 GPIO 39 set GPSR1_40 0 GPIO 40 set GPSR1_41 0 GPIO 41 set GPSR1_42 0 GPIO 42 set GPSR1_43 0 GPIO 43 set GPSR1_44 0 GPIO 44 set GPSR1_45 0 GPIO 45 set GPSR1_46 0 GPIO 46 set GPSR1_47 0 GPIO 47 set GPSR1_48 0 GPIO 48 set GPSR1_49 0 GPIO 49 set GPSR1_50 0 GPIO 50 set GPSR1_51 0 GPIO 51 set GPSR1_52 0 GPIO 52 set GPSR1_53 0 GPIO 53 set GPSR1_54 0 GPIO 54 set GPSR1_55 0 GPIO 55 set GPSR1_56 0 GPIO 56 set GPSR1_57 0 GPIO 57 set GPSR1_58 0 GPIO 58 set GPSR1_59 0 GPIO 59 set GPSR1_60 0 GPIO 60 set GPSR1_61 0 GPIO 61 set GPSR1_62 0 GPIO 62 set GPSR1_63 0 GPIO 63 set GPIO Set Register 2 (4-11) GPSR2 0x00000000 00000000 00000000 00000000 00000000 GPSR2_64 0 GPIO 64 set GPSR2_65 0 GPIO 65 set GPSR2_66 0 GPIO 66 set GPSR2_67 0 GPIO 67 set GPSR2_68 0 GPIO 68 set GPSR2_69 0 GPIO 69 set GPSR2_70 0 GPIO 70 set GPSR2_71 0 GPIO 71 set GPSR2_72 0 GPIO 72 set GPSR2_73 0 GPIO 73 set GPSR2_74 0 GPIO 74 set GPSR2_75 0 GPIO 75 set GPSR2_76 0 GPIO 76 set GPSR2_77 0 GPIO 77 set GPSR2_78 0 GPIO 78 set GPSR2_79 0 GPIO 79 set GPSR2_80 0 GPIO 80 set GPSR2_81 0 GPIO 81 set GPSR2_82 0 GPIO 82 set GPSR2_83 0 GPIO 83 set GPSR2_84 0 GPIO 84 set GPSR2_85 0 GPIO 85 set GPSR2_86 0 GPIO 86 set GPSR2_87 0 GPIO 87 set GPSR2_88 0 GPIO 88 set GPSR2_89 0 GPIO 89 set GPSR2_90 0 GPIO 90 set GPSR2_91 0 GPIO 91 set GPSR2_92 0 GPIO 92 set GPSR2_93 0 GPIO 93 set GPSR2_94 0 GPIO 94 set GPSR2_95 0 GPIO 95 set GPIO Set Register 3 (96-120) GPSR3 0x00000000 00000000 00000000 00000000 00000000 GPSR3_96 0 GPIO 96 set GPSR3_97 0 GPIO 97 set GPSR3_98 0 GPIO 98 set GPSR3_99 0 GPIO 99 set GPSR3_100 0 GPIO 100 set GPSR3_101 0 GPIO 101 set GPSR3_102 0 GPIO 102 set GPSR3_103 0 GPIO 103 set GPSR3_104 0 GPIO 104 set GPSR3_105 0 GPIO 105 set GPSR3_106 0 GPIO 106 set GPSR3_107 0 GPIO 107 set GPSR3_108 0 GPIO 108 set GPSR3_109 0 GPIO 109 set GPSR3_110 0 GPIO 110 set GPSR3_111 0 GPIO 111 set GPSR3_112 0 GPIO 112 set GPSR3_113 0 GPIO 113 set GPSR3_114 0 GPIO 114 set GPSR3_115 0 GPIO 115 set GPSR3_116 0 GPIO 116 set GPSR3_117 0 GPIO 117 set GPSR3_118 0 GPIO 118 set GPSR3_119 0 GPIO 119 set GPSR3_120 0 GPIO 120 set GPIO Clear Register 0 (4-11) GPCR0 0x00000000 00000000 00000000 00000000 00000000 GPCR0_0 0 GPIO 0 clear GPCR0_1 0 GPIO 1 clear GPCR0_2 0 GPIO 2 clear GPCR0_3 0 GPIO 3 clear GPCR0_4 0 GPIO 4 clear GPCR0_5 0 GPIO 5 clear GPCR0_6 0 GPIO 6 clear GPCR0_7 0 GPIO 7 clear GPCR0_8 0 GPIO 8 clear GPCR0_9 0 GPIO 9 clear GPCR0_10 0 GPIO 10 clear GPCR0_11 0 GPIO 11 clear GPCR0_12 0 GPIO 12 clear GPCR0_13 0 GPIO 13 clear GPCR0_14 0 GPIO 14 clear GPCR0_15 0 GPIO 15 clear GPCR0_16 0 GPIO 16 clear GPCR0_17 0 GPIO 17 clear GPCR0_18 0 GPIO 18 clear GPCR0_19 0 GPIO 19 clear GPCR0_20 0 GPIO 20 clear GPCR0_21 0 GPIO 21 clear GPCR0_22 0 GPIO 22 clear GPCR0_23 0 GPIO 23 clear GPCR0_24 0 GPIO 24 clear GPCR0_25 0 GPIO 25 clear GPCR0_26 0 GPIO 26 clear GPCR0_27 0 GPIO 27 clear GPCR0_28 0 GPIO 28 clear GPCR0_29 0 GPIO 29 clear GPCR0_30 0 GPIO 30 clear GPCR0_31 0 GPIO 31 clear GPIO Clear Register 1 (4-11) GPCR1 0x00000000 00000000 00000000 00000000 00000000 GPCR1_32 0 GPIO 32 clear GPCR1_33 0 GPIO 33 clear GPCR1_34 0 GPIO 34 clear GPCR1_35 0 GPIO 35 clear GPCR1_36 0 GPIO 36 clear GPCR1_37 0 GPIO 37 clear GPCR1_38 0 GPIO 38 clear GPCR1_39 0 GPIO 39 clear GPCR1_40 0 GPIO 40 clear GPCR1_41 0 GPIO 41 clear GPCR1_42 0 GPIO 42 clear GPCR1_43 0 GPIO 43 clear GPCR1_44 0 GPIO 44 clear GPCR1_45 0 GPIO 45 clear GPCR1_46 0 GPIO 46 clear GPCR1_47 0 GPIO 47 clear GPCR1_48 0 GPIO 48 clear GPCR1_49 0 GPIO 49 clear GPCR1_50 0 GPIO 50 clear GPCR1_51 0 GPIO 51 clear GPCR1_52 0 GPIO 52 clear GPCR1_53 0 GPIO 53 clear GPCR1_54 0 GPIO 54 clear GPCR1_55 0 GPIO 55 clear GPCR1_56 0 GPIO 56 clear GPCR1_57 0 GPIO 57 clear GPCR1_58 0 GPIO 58 clear GPCR1_59 0 GPIO 59 clear GPCR1_60 0 GPIO 60 clear GPCR1_61 0 GPIO 61 clear GPCR1_62 0 GPIO 62 clear GPCR1_63 0 GPIO 63 clear GPIO Clear Register 2 (4-12) GPCR2 0x00000000 00000000 00000000 00000000 00000000 GPCR2_64 0 GPIO 64 clear GPCR2_65 0 GPIO 65 clear GPCR2_66 0 GPIO 66 clear GPCR2_67 0 GPIO 67 clear GPCR2_68 0 GPIO 68 clear GPCR2_69 0 GPIO 69 clear GPCR2_70 0 GPIO 70 clear GPCR2_71 0 GPIO 71 clear GPCR2_72 0 GPIO 72 clear GPCR2_73 0 GPIO 73 clear GPCR2_74 0 GPIO 74 clear GPCR2_75 0 GPIO 75 clear GPCR2_76 0 GPIO 76 clear GPCR2_77 0 GPIO 77 clear GPCR2_78 0 GPIO 78 clear GPCR2_79 0 GPIO 79 clear GPCR2_80 0 GPIO 80 clear GPCR2_81 0 GPIO 81 clear GPCR2_82 0 GPIO 82 clear GPCR2_83 0 GPIO 83 clear GPCR2_84 0 GPIO 84 clear GPCR2_85 0 GPIO 85 clear GPCR2_86 0 GPIO 86 clear GPCR2_87 0 GPIO 87 clear GPCR2_88 0 GPIO 88 clear GPCR2_89 0 GPIO 89 clear GPCR2_90 0 GPIO 90 clear GPCR2_91 0 GPIO 91 clear GPCR2_92 0 GPIO 92 clear GPCR2_93 0 GPIO 93 clear GPCR2_94 0 GPIO 94 clear GPCR2_95 0 GPIO 95 clear GPIO Clear Register 3 (96-120) GPCR3 0x00000000 00000000 00000000 00000000 00000000 GPCR3_96 0 GPIO 96 clear GPCR3_97 0 GPIO 97 clear GPCR3_98 0 GPIO 98 clear GPCR3_99 0 GPIO 99 clear GPCR3_100 0 GPIO 100 clear GPCR3_101 0 GPIO 101 clear GPCR3_102 0 GPIO 102 clear GPCR3_103 0 GPIO 103 clear GPCR3_104 0 GPIO 104 clear GPCR3_105 0 GPIO 105 clear GPCR3_106 0 GPIO 106 clear GPCR3_107 0 GPIO 107 clear GPCR3_108 0 GPIO 108 clear GPCR3_109 0 GPIO 109 clear GPCR3_110 0 GPIO 110 clear GPCR3_111 0 GPIO 111 clear GPCR3_112 0 GPIO 112 clear GPCR3_113 0 GPIO 113 clear GPCR3_114 0 GPIO 114 clear GPCR3_115 0 GPIO 115 clear GPCR3_116 0 GPIO 116 clear GPCR3_117 0 GPIO 117 clear GPCR3_118 0 GPIO 118 clear GPCR3_119 0 GPIO 119 clear GPCR3_120 0 GPIO 120 clear GPIO Raising Edge Detect Enable Register 0 (4-13) GRER0 0x00000003 00000000 00000000 00000000 00000011 GRER0_0 1 GPIO 0 raising edge detect enabled GRER0_1 1 GPIO 1 raising edge detect enabled GRER0_2 0 GPIO 2 raising edge detect enabled GRER0_3 0 GPIO 3 raising edge detect enabled GRER0_4 0 GPIO 4 raising edge detect enabled GRER0_5 0 GPIO 5 raising edge detect enabled GRER0_6 0 GPIO 6 raising edge detect enabled GRER0_7 0 GPIO 7 raising edge detect enabled GRER0_8 0 GPIO 8 raising edge detect enabled GRER0_9 0 GPIO 9 raising edge detect enabled GRER0_10 0 GPIO 10 raising edge detect enabled GRER0_11 0 GPIO 11 raising edge detect enabled GRER0_12 0 GPIO 12 raising edge detect enabled GRER0_13 0 GPIO 13 raising edge detect enabled GRER0_14 0 GPIO 14 raising edge detect enabled GRER0_15 0 GPIO 15 raising edge detect enabled GRER0_16 0 GPIO 16 raising edge detect enabled GRER0_17 0 GPIO 17 raising edge detect enabled GRER0_18 0 GPIO 18 raising edge detect enabled GRER0_19 0 GPIO 19 raising edge detect enabled GRER0_20 0 GPIO 20 raising edge detect enabled GRER0_21 0 GPIO 21 raising edge detect enabled GRER0_22 0 GPIO 22 raising edge detect enabled GRER0_23 0 GPIO 23 raising edge detect enabled GRER0_24 0 GPIO 24 raising edge detect enabled GRER0_25 0 GPIO 25 raising edge detect enabled GRER0_26 0 GPIO 26 raising edge detect enabled GRER0_27 0 GPIO 27 raising edge detect enabled GRER0_28 0 GPIO 28 raising edge detect enabled GRER0_29 0 GPIO 29 raising edge detect enabled GRER0_30 0 GPIO 30 raising edge detect enabled GRER0_31 0 GPIO 31 raising edge detect enabled GPIO Raising Edge Detect Enable Register 1 (4-13) GRER1 0x00000020 00000000 00000000 00000000 00100000 GRER1_32 0 GPIO 32 raising edge detect enabled GRER1_33 0 GPIO 33 raising edge detect enabled GRER1_34 0 GPIO 34 raising edge detect enabled GRER1_35 0 GPIO 35 raising edge detect enabled GRER1_36 0 GPIO 36 raising edge detect enabled GRER1_37 1 GPIO 37 raising edge detect enabled GRER1_38 0 GPIO 38 raising edge detect enabled GRER1_39 0 GPIO 39 raising edge detect enabled GRER1_40 0 GPIO 40 raising edge detect enabled GRER1_41 0 GPIO 41 raising edge detect enabled GRER1_42 0 GPIO 42 raising edge detect enabled GRER1_43 0 GPIO 43 raising edge detect enabled GRER1_44 0 GPIO 44 raising edge detect enabled GRER1_45 0 GPIO 45 raising edge detect enabled GRER1_46 0 GPIO 46 raising edge detect enabled GRER1_47 0 GPIO 47 raising edge detect enabled GRER1_48 0 GPIO 48 raising edge detect enabled GRER1_49 0 GPIO 49 raising edge detect enabled GRER1_50 0 GPIO 50 raising edge detect enabled GRER1_51 0 GPIO 51 raising edge detect enabled GRER1_52 0 GPIO 52 raising edge detect enabled GRER1_53 0 GPIO 53 raising edge detect enabled GRER1_54 0 GPIO 54 raising edge detect enabled GRER1_55 0 GPIO 55 raising edge detect enabled GRER1_56 0 GPIO 56 raising edge detect enabled GRER1_57 0 GPIO 57 raising edge detect enabled GRER1_58 0 GPIO 58 raising edge detect enabled GRER1_59 0 GPIO 59 raising edge detect enabled GRER1_60 0 GPIO 60 raising edge detect enabled GRER1_61 0 GPIO 61 raising edge detect enabled GRER1_62 0 GPIO 62 raising edge detect enabled GRER1_63 0 GPIO 63 raising edge detect enabled GPIO Raising Edge Detect Enable Register 2 (4-13) GRER2 0x00000000 00000000 00000000 00000000 00000000 GRER2_64 0 GPIO 64 raising edge detect enabled GRER2_65 0 GPIO 65 raising edge detect enabled GRER2_66 0 GPIO 66 raising edge detect enabled GRER2_67 0 GPIO 67 raising edge detect enabled GRER2_68 0 GPIO 68 raising edge detect enabled GRER2_69 0 GPIO 69 raising edge detect enabled GRER2_70 0 GPIO 70 raising edge detect enabled GRER2_71 0 GPIO 71 raising edge detect enabled GRER2_72 0 GPIO 72 raising edge detect enabled GRER2_73 0 GPIO 73 raising edge detect enabled GRER2_74 0 GPIO 74 raising edge detect enabled GRER2_75 0 GPIO 75 raising edge detect enabled GRER2_76 0 GPIO 76 raising edge detect enabled GRER2_77 0 GPIO 77 raising edge detect enabled GRER2_78 0 GPIO 78 raising edge detect enabled GRER2_79 0 GPIO 79 raising edge detect enabled GRER2_80 0 GPIO 80 raising edge detect enabled GRER2_81 0 GPIO 81 raising edge detect enabled GRER2_82 0 GPIO 82 raising edge detect enabled GRER2_83 0 GPIO 83 raising edge detect enabled GRER2_84 0 GPIO 84 raising edge detect enabled GRER2_85 0 GPIO 85 raising edge detect enabled GRER2_86 0 GPIO 86 raising edge detect enabled GRER2_87 0 GPIO 87 raising edge detect enabled GRER2_88 0 GPIO 88 raising edge detect enabled GRER2_89 0 GPIO 89 raising edge detect enabled GRER2_90 0 GPIO 90 raising edge detect enabled GRER2_91 0 GPIO 91 raising edge detect enabled GRER2_92 0 GPIO 92 raising edge detect enabled GRER2_93 0 GPIO 93 raising edge detect enabled GRER2_94 0 GPIO 94 raising edge detect enabled GRER2_95 0 GPIO 95 raising edge detect enabled GPIO Raising Edge Detect Enable Register 3 (96-120) GRER3 0x00000005 00000000 00000000 00000000 00000101 GRER3_96 1 GPIO 96 raising edge detect enabled GRER3_97 0 GPIO 97 raising edge detect enabled GRER3_98 1 GPIO 98 raising edge detect enabled GRER3_99 0 GPIO 99 raising edge detect enabled GRER3_100 0 GPIO 100 raising edge detect enabled GRER3_101 0 GPIO 101 raising edge detect enabled GRER3_102 0 GPIO 102 raising edge detect enabled GRER3_103 0 GPIO 103 raising edge detect enabled GRER3_104 0 GPIO 104 raising edge detect enabled GRER3_105 0 GPIO 105 raising edge detect enabled GRER3_106 0 GPIO 106 raising edge detect enabled GRER3_107 0 GPIO 107 raising edge detect enabled GRER3_108 0 GPIO 108 raising edge detect enabled GRER3_109 0 GPIO 109 raising edge detect enabled GRER3_110 0 GPIO 110 raising edge detect enabled GRER3_111 0 GPIO 111 raising edge detect enabled GRER3_112 0 GPIO 112 raising edge detect enabled GRER3_113 0 GPIO 113 raising edge detect enabled GRER3_114 0 GPIO 114 raising edge detect enabled GRER3_115 0 GPIO 115 raising edge detect enabled GRER3_116 0 GPIO 116 raising edge detect enabled GRER3_117 0 GPIO 117 raising edge detect enabled GRER3_118 0 GPIO 118 raising edge detect enabled GRER3_119 0 GPIO 119 raising edge detect enabled GRER3_120 0 GPIO 120 raising edge detect enabled GPIO Falling Edge Detect Enable Register 0 (4-14) GFER0 0x00000003 00000000 00000000 00000000 00000011 GFER0_0 1 GPIO 0 falling edge detect enabled GFER0_1 1 GPIO 1 falling edge detect enabled GFER0_2 0 GPIO 2 falling edge detect enabled GFER0_3 0 GPIO 3 falling edge detect enabled GFER0_4 0 GPIO 4 falling edge detect enabled GFER0_5 0 GPIO 5 falling edge detect enabled GFER0_6 0 GPIO 6 falling edge detect enabled GFER0_7 0 GPIO 7 falling edge detect enabled GFER0_8 0 GPIO 8 falling edge detect enabled GFER0_9 0 GPIO 9 falling edge detect enabled GFER0_10 0 GPIO 10 falling edge detect enabled GFER0_11 0 GPIO 11 falling edge detect enabled GFER0_12 0 GPIO 12 falling edge detect enabled GFER0_13 0 GPIO 13 falling edge detect enabled GFER0_14 0 GPIO 14 falling edge detect enabled GFER0_15 0 GPIO 15 falling edge detect enabled GFER0_16 0 GPIO 16 falling edge detect enabled GFER0_17 0 GPIO 17 falling edge detect enabled GFER0_18 0 GPIO 18 falling edge detect enabled GFER0_19 0 GPIO 19 falling edge detect enabled GFER0_20 0 GPIO 20 falling edge detect enabled GFER0_21 0 GPIO 21 falling edge detect enabled GFER0_22 0 GPIO 22 falling edge detect enabled GFER0_23 0 GPIO 23 falling edge detect enabled GFER0_24 0 GPIO 24 falling edge detect enabled GFER0_25 0 GPIO 25 falling edge detect enabled GFER0_26 0 GPIO 26 falling edge detect enabled GFER0_27 0 GPIO 27 falling edge detect enabled GFER0_28 0 GPIO 28 falling edge detect enabled GFER0_29 0 GPIO 29 falling edge detect enabled GFER0_30 0 GPIO 30 falling edge detect enabled GFER0_31 0 GPIO 31 falling edge detect enabled GPIO Falling Edge Detect Enable Register 1 (4-14) GFER1 0x00000030 00000000 00000000 00000000 00110000 GFER1_32 0 GPIO 32 falling edge detect enabled GFER1_33 0 GPIO 33 falling edge detect enabled GFER1_34 0 GPIO 34 falling edge detect enabled GFER1_35 0 GPIO 35 falling edge detect enabled GFER1_36 1 GPIO 36 falling edge detect enabled GFER1_37 1 GPIO 37 falling edge detect enabled GFER1_38 0 GPIO 38 falling edge detect enabled GFER1_39 0 GPIO 39 falling edge detect enabled GFER1_40 0 GPIO 40 falling edge detect enabled GFER1_41 0 GPIO 41 falling edge detect enabled GFER1_42 0 GPIO 42 falling edge detect enabled GFER1_43 0 GPIO 43 falling edge detect enabled GFER1_44 0 GPIO 44 falling edge detect enabled GFER1_45 0 GPIO 45 falling edge detect enabled GFER1_46 0 GPIO 46 falling edge detect enabled GFER1_47 0 GPIO 47 falling edge detect enabled GFER1_48 0 GPIO 48 falling edge detect enabled GFER1_49 0 GPIO 49 falling edge detect enabled GFER1_50 0 GPIO 50 falling edge detect enabled GFER1_51 0 GPIO 51 falling edge detect enabled GFER1_52 0 GPIO 52 falling edge detect enabled GFER1_53 0 GPIO 53 falling edge detect enabled GFER1_54 0 GPIO 54 falling edge detect enabled GFER1_55 0 GPIO 55 falling edge detect enabled GFER1_56 0 GPIO 56 falling edge detect enabled GFER1_57 0 GPIO 57 falling edge detect enabled GFER1_58 0 GPIO 58 falling edge detect enabled GFER1_59 0 GPIO 59 falling edge detect enabled GFER1_60 0 GPIO 60 falling edge detect enabled GFER1_61 0 GPIO 61 falling edge detect enabled GFER1_62 0 GPIO 62 falling edge detect enabled GFER1_63 0 GPIO 63 falling edge detect enabled GPIO Falling Edge Detect Enable Register 2 (4-14) GFER2 0x00000000 00000000 00000000 00000000 00000000 GFER2_64 0 GPIO 64 falling edge detect enabled GFER2_65 0 GPIO 65 falling edge detect enabled GFER2_66 0 GPIO 66 falling edge detect enabled GFER2_67 0 GPIO 67 falling edge detect enabled GFER2_68 0 GPIO 68 falling edge detect enabled GFER2_69 0 GPIO 69 falling edge detect enabled GFER2_70 0 GPIO 70 falling edge detect enabled GFER2_71 0 GPIO 71 falling edge detect enabled GFER2_72 0 GPIO 72 falling edge detect enabled GFER2_73 0 GPIO 73 falling edge detect enabled GFER2_74 0 GPIO 74 falling edge detect enabled GFER2_75 0 GPIO 75 falling edge detect enabled GFER2_76 0 GPIO 76 falling edge detect enabled GFER2_77 0 GPIO 77 falling edge detect enabled GFER2_78 0 GPIO 78 falling edge detect enabled GFER2_79 0 GPIO 79 falling edge detect enabled GFER2_80 0 GPIO 80 falling edge detect enabled GFER2_81 0 GPIO 81 falling edge detect enabled GFER2_82 0 GPIO 82 falling edge detect enabled GFER2_83 0 GPIO 83 falling edge detect enabled GFER2_84 0 GPIO 84 falling edge detect enabled GFER2_85 0 GPIO 85 falling edge detect enabled GFER2_86 0 GPIO 86 falling edge detect enabled GFER2_87 0 GPIO 87 falling edge detect enabled GFER2_88 0 GPIO 88 falling edge detect enabled GFER2_89 0 GPIO 89 falling edge detect enabled GFER2_90 0 GPIO 90 falling edge detect enabled GFER2_91 0 GPIO 91 falling edge detect enabled GFER2_92 0 GPIO 92 falling edge detect enabled GFER2_93 0 GPIO 93 falling edge detect enabled GFER2_94 0 GPIO 94 falling edge detect enabled GFER2_95 0 GPIO 95 falling edge detect enabled GPIO Falling Edge Detect Enable Register 3 (96-120) GFER3 0x00000005 00000000 00000000 00000000 00000101 GFER3_96 1 GPIO 96 falling edge detect enabled GFER3_97 0 GPIO 97 falling edge detect enabled GFER3_98 1 GPIO 98 falling edge detect enabled GFER3_99 0 GPIO 99 falling edge detect enabled GFER3_100 0 GPIO 100 falling edge detect enabled GFER3_101 0 GPIO 101 falling edge detect enabled GFER3_102 0 GPIO 102 falling edge detect enabled GFER3_103 0 GPIO 103 falling edge detect enabled GFER3_104 0 GPIO 104 falling edge detect enabled GFER3_105 0 GPIO 105 falling edge detect enabled GFER3_106 0 GPIO 106 falling edge detect enabled GFER3_107 0 GPIO 107 falling edge detect enabled GFER3_108 0 GPIO 108 falling edge detect enabled GFER3_109 0 GPIO 109 falling edge detect enabled GFER3_110 0 GPIO 110 falling edge detect enabled GFER3_111 0 GPIO 111 falling edge detect enabled GFER3_112 0 GPIO 112 falling edge detect enabled GFER3_113 0 GPIO 113 falling edge detect enabled GFER3_114 0 GPIO 114 falling edge detect enabled GFER3_115 0 GPIO 115 falling edge detect enabled GFER3_116 0 GPIO 116 falling edge detect enabled GFER3_117 0 GPIO 117 falling edge detect enabled GFER3_118 0 GPIO 118 falling edge detect enabled GFER3_119 0 GPIO 119 falling edge detect enabled GFER3_120 0 GPIO 120 falling edge detect enabled GPIO Edge Detect Register 0 (4-15) GEDR0 0x00000000 00000000 00000000 00000000 00000000 GEDR0_0 0 GPIO 0 edge detected GEDR0_1 0 GPIO 1 edge detected GEDR0_2 0 GPIO 2 edge detected GEDR0_3 0 GPIO 3 edge detected GEDR0_4 0 GPIO 4 edge detected GEDR0_5 0 GPIO 5 edge detected GEDR0_6 0 GPIO 6 edge detected GEDR0_7 0 GPIO 7 edge detected GEDR0_8 0 GPIO 8 edge detected GEDR0_9 0 GPIO 9 edge detected GEDR0_10 0 GPIO 10 edge detected GEDR0_11 0 GPIO 11 edge detected GEDR0_12 0 GPIO 12 edge detected GEDR0_13 0 GPIO 13 edge detected GEDR0_14 0 GPIO 14 edge detected GEDR0_15 0 GPIO 15 edge detected GEDR0_16 0 GPIO 16 edge detected GEDR0_17 0 GPIO 17 edge detected GEDR0_18 0 GPIO 18 edge detected GEDR0_19 0 GPIO 19 edge detected GEDR0_20 0 GPIO 20 edge detected GEDR0_21 0 GPIO 21 edge detected GEDR0_22 0 GPIO 22 edge detected GEDR0_23 0 GPIO 23 edge detected GEDR0_24 0 GPIO 24 edge detected GEDR0_25 0 GPIO 25 edge detected GEDR0_26 0 GPIO 26 edge detected GEDR0_27 0 GPIO 27 edge detected GEDR0_28 0 GPIO 28 edge detected GEDR0_29 0 GPIO 29 edge detected GEDR0_30 0 GPIO 30 edge detected GEDR0_31 0 GPIO 31 edge detected GPIO Edge Detect Register 1 (4-16) GEDR1 0x00000000 00000000 00000000 00000000 00000000 GEDR1_32 0 GPIO 32 edge detected GEDR1_33 0 GPIO 33 edge detected GEDR1_34 0 GPIO 34 edge detected GEDR1_35 0 GPIO 35 edge detected GEDR1_36 0 GPIO 36 edge detected GEDR1_37 0 GPIO 37 edge detected GEDR1_38 0 GPIO 38 edge detected GEDR1_39 0 GPIO 39 edge detected GEDR1_40 0 GPIO 40 edge detected GEDR1_41 0 GPIO 41 edge detected GEDR1_42 0 GPIO 42 edge detected GEDR1_43 0 GPIO 43 edge detected GEDR1_44 0 GPIO 44 edge detected GEDR1_45 0 GPIO 45 edge detected GEDR1_46 0 GPIO 46 edge detected GEDR1_47 0 GPIO 47 edge detected GEDR1_48 0 GPIO 48 edge detected GEDR1_49 0 GPIO 49 edge detected GEDR1_50 0 GPIO 50 edge detected GEDR1_51 0 GPIO 51 edge detected GEDR1_52 0 GPIO 52 edge detected GEDR1_53 0 GPIO 53 edge detected GEDR1_54 0 GPIO 54 edge detected GEDR1_55 0 GPIO 55 edge detected GEDR1_56 0 GPIO 56 edge detected GEDR1_57 0 GPIO 57 edge detected GEDR1_58 0 GPIO 58 edge detected GEDR1_59 0 GPIO 59 edge detected GEDR1_60 0 GPIO 60 edge detected GEDR1_61 0 GPIO 61 edge detected GEDR1_62 0 GPIO 62 edge detected GEDR1_63 0 GPIO 63 edge detected GPIO Edge Detect Register 2 (4-16) GEDR2 0x00000000 00000000 00000000 00000000 00000000 GEDR2_64 0 GPIO 64 edge detected GEDR2_65 0 GPIO 65 edge detected GEDR2_66 0 GPIO 66 edge detected GEDR2_67 0 GPIO 67 edge detected GEDR2_68 0 GPIO 68 edge detected GEDR2_69 0 GPIO 69 edge detected GEDR2_70 0 GPIO 70 edge detected GEDR2_71 0 GPIO 71 edge detected GEDR2_72 0 GPIO 72 edge detected GEDR2_73 0 GPIO 73 edge detected GEDR2_74 0 GPIO 74 edge detected GEDR2_75 0 GPIO 75 edge detected GEDR2_76 0 GPIO 76 edge detected GEDR2_77 0 GPIO 77 edge detected GEDR2_78 0 GPIO 78 edge detected GEDR2_79 0 GPIO 79 edge detected GEDR2_80 0 GPIO 80 edge detected GEDR2_81 0 GPIO 81 edge detected GEDR2_82 0 GPIO 82 edge detected GEDR2_83 0 GPIO 83 edge detected GEDR2_84 0 GPIO 84 edge detected GEDR2_85 0 GPIO 85 edge detected GEDR2_86 0 GPIO 86 edge detected GEDR2_87 0 GPIO 87 edge detected GEDR2_88 0 GPIO 88 edge detected GEDR2_89 0 GPIO 89 edge detected GEDR2_90 0 GPIO 90 edge detected GEDR2_91 0 GPIO 91 edge detected GEDR2_92 0 GPIO 92 edge detected GEDR2_93 0 GPIO 93 edge detected GEDR2_94 0 GPIO 94 edge detected GEDR2_95 0 GPIO 95 edge detected GPIO GPIO Edge Detect Register 3 (96-120) GEDR3 0x00000005 00000000 00000000 00000000 00000101 GEDR3_96 1 GPIO 96 edge detected GEDR3_97 0 GPIO 97 edge detected GEDR3_98 1 GPIO 98 edge detected GEDR3_99 0 GPIO 99 edge detected GEDR3_100 0 GPIO 100 edge detected GEDR3_101 0 GPIO 101 edge detected GEDR3_102 0 GPIO 102 edge detected GEDR3_103 0 GPIO 103 edge detected GEDR3_104 0 GPIO 104 edge detected GEDR3_105 0 GPIO 105 edge detected GEDR3_106 0 GPIO 106 edge detected GEDR3_107 0 GPIO 107 edge detected GEDR3_108 0 GPIO 108 edge detected GEDR3_109 0 GPIO 109 edge detected GEDR3_110 0 GPIO 110 edge detected GEDR3_111 0 GPIO 111 edge detected GEDR3_112 0 GPIO 112 edge detected GEDR3_113 0 GPIO 113 edge detected GEDR3_114 0 GPIO 114 edge detected GEDR3_115 0 GPIO 115 edge detected GEDR3_116 0 GPIO 116 edge detected GEDR3_117 0 GPIO 117 edge detected GEDR3_118 0 GPIO 118 edge detected GEDR3_119 0 GPIO 119 edge detected GEDR3_120 0 GPIO 120 edge detected GPIO Alternate Function Register 0 Lower (4-17) GAFR0L 0x06800140 00000110 10000000 00000001 01000000 GAFR0L_0 0 GPIO 0 alternate function select GAFR0L_1 0 GPIO 1 alternate function select GAFR0L_2 0 GPIO 2 alternate function select GAFR0L_3 1 GPIO 3 alternate function select GAFR0L_4 1 GPIO 4 alternate function select GAFR0L_5 0 GPIO 5 alternate function select GAFR0L_6 0 GPIO 6 alternate function select GAFR0L_7 0 GPIO 7 alternate function select GAFR0L_8 0 GPIO 8 alternate function select GAFR0L_9 0 GPIO 9 alternate function select GAFR0L_10 0 GPIO 10 alternate function select GAFR0L_11 2 GPIO 11 alternate function select GAFR0L_12 2 GPIO 12 alternate function select GAFR0L_13 1 GPIO 13 alternate function select GAFR0L_14 0 GPIO 14 alternate function select GAFR0L_15 0 GPIO 15 alternate function select GPIO Alternate Function Register 0 Upper (4-18) GAFR0U 0x5918b005 01011001 00011000 10110000 00000101 GAFR0U_16 1 GPIO 16 alternate function select GAFR0U_17 1 GPIO 17 alternate function select GAFR0U_18 0 GPIO 18 alternate function select GAFR0U_19 0 GPIO 19 alternate function select GAFR0U_20 0 GPIO 20 alternate function select GAFR0U_21 0 GPIO 21 alternate function select GAFR0U_22 3 GPIO 22 alternate function select GAFR0U_23 2 GPIO 23 alternate function select GAFR0U_24 0 GPIO 24 alternate function select GAFR0U_25 2 GPIO 25 alternate function select GAFR0U_26 1 GPIO 26 alternate function select GAFR0U_27 0 GPIO 27 alternate function select GAFR0U_28 1 GPIO 28 alternate function select GAFR0U_29 2 GPIO 29 alternate function select GAFR0U_30 1 GPIO 30 alternate function select GAFR0U_31 1 GPIO 31 alternate function select GPIO Alternate Function Register 1 Lower (4-18) GAFR1L 0x609520a2 01100000 10010101 00100000 10100010 GAFR1L_32 2 GPIO 32 alternate function select GAFR1L_33 0 GPIO 33 alternate function select GAFR1L_34 2 GPIO 34 alternate function select GAFR1L_35 2 GPIO 35 alternate function select GAFR1L_36 0 GPIO 36 alternate function select GAFR1L_37 0 GPIO 37 alternate function select GAFR1L_38 2 GPIO 38 alternate function select GAFR1L_39 0 GPIO 39 alternate function select GAFR1L_40 1 GPIO 40 alternate function select GAFR1L_41 1 GPIO 41 alternate function select GAFR1L_42 1 GPIO 42 alternate function select GAFR1L_43 2 GPIO 43 alternate function select GAFR1L_44 0 GPIO 44 alternate function select GAFR1L_45 0 GPIO 45 alternate function select GAFR1L_46 2 GPIO 46 alternate function select GAFR1L_47 1 GPIO 47 alternate function select GPIO Alternate Function Register 1 Upper (4-19) GAFR1U 0xaaa00000 10101010 10100000 00000000 00000000 GAFR1U_48 0 GPIO 48 alternate function select GAFR1U_49 0 GPIO 49 alternate function select GAFR1U_50 0 GPIO 50 alternate function select GAFR1U_51 0 GPIO 51 alternate function select GAFR1U_52 0 GPIO 52 alternate function select GAFR1U_53 0 GPIO 53 alternate function select GAFR1U_54 0 GPIO 54 alternate function select GAFR1U_55 0 GPIO 55 alternate function select GAFR1U_56 0 GPIO 56 alternate function select GAFR1U_57 0 GPIO 57 alternate function select GAFR1U_58 2 GPIO 58 alternate function select GAFR1U_59 2 GPIO 59 alternate function select GAFR1U_60 2 GPIO 60 alternate function select GAFR1U_61 2 GPIO 61 alternate function select GAFR1U_62 2 GPIO 62 alternate function select GAFR1U_63 2 GPIO 63 alternate function select GPIO Alternate Function Register 2 Lower (4-19) GAFR2L 0x0aaaaaaa 00001010 10101010 10101010 10101010 GAFR2L_64 2 GPIO 64 alternate function select GAFR2L_65 2 GPIO 65 alternate function select GAFR2L_66 2 GPIO 66 alternate function select GAFR2L_67 2 GPIO 67 alternate function select GAFR2L_68 2 GPIO 68 alternate function select GAFR2L_69 2 GPIO 69 alternate function select GAFR2L_70 2 GPIO 70 alternate function select GAFR2L_71 2 GPIO 71 alternate function select GAFR2L_72 2 GPIO 72 alternate function select GAFR2L_73 2 GPIO 73 alternate function select GAFR2L_74 2 GPIO 74 alternate function select GAFR2L_75 2 GPIO 75 alternate function select GAFR2L_76 2 GPIO 76 alternate function select GAFR2L_77 2 GPIO 77 alternate function select GAFR2L_78 0 GPIO 78 alternate function select GAFR2L_79 0 GPIO 79 alternate function select GPIO Alternate Function Register 2 Upper (4-19) GAFR2U 0x01000000 00000001 00000000 00000000 00000000 GAFR2U_80 0 GPIO 80 alternate function select GAFR2U_81 0 GPIO 81 alternate function select GAFR2U_82 0 GPIO 82 alternate function select GAFR2U_83 0 GPIO 83 alternate function select GAFR2U_84 0 GPIO 84 alternate function select GAFR2U_85 0 GPIO 85 alternate function select GAFR2U_86 0 GPIO 86 alternate function select GAFR2U_87 0 GPIO 87 alternate function select GAFR2U_88 0 GPIO 88 alternate function select GAFR2U_89 0 GPIO 89 alternate function select GAFR2U_90 0 GPIO 90 alternate function select GAFR2U_91 0 GPIO 91 alternate function select GAFR2U_92 1 GPIO 92 alternate function select GAFR2U_93 0 GPIO 93 alternate function select GAFR2U_94 0 GPIO 94 alternate function select GAFR2U_95 0 GPIO 95 alternate function select GPIO Alternate Function Register 3 Lower (96-111) GAFR3L 0x56aa9500 01010110 10101010 10010101 00000000 GAFR3L_96 0 GPIO 96 alternate function select GAFR3L_97 0 GPIO 97 alternate function select GAFR3L_98 0 GPIO 98 alternate function select GAFR3L_99 0 GPIO 99 alternate function select GAFR3L_100 1 GPIO 100 alternate function select GAFR3L_101 1 GPIO 101 alternate function select GAFR3L_102 1 GPIO 102 alternate function select GAFR3L_103 2 GPIO 103 alternate function select GAFR3L_104 2 GPIO 104 alternate function select GAFR3L_105 2 GPIO 105 alternate function select GAFR3L_106 2 GPIO 106 alternate function select GAFR3L_107 2 GPIO 107 alternate function select GAFR3L_108 2 GPIO 108 alternate function select GAFR3L_109 1 GPIO 109 alternate function select GAFR3L_110 1 GPIO 110 alternate function select GAFR3L_111 1 GPIO 111 alternate function select GPIO Alternate Function Register 3 Upper (112-120) GAFR3U 0x000014c5 00000000 00000000 00010100 11000101 GAFR3L_112 1 GPIO 112 alternate function select GAFR3L_113 1 GPIO 113 alternate function select GAFR3L_114 0 GPIO 114 alternate function select GAFR3L_115 3 GPIO 115 alternate function select GAFR3L_116 0 GPIO 116 alternate function select GAFR3L_117 1 GPIO 117 alternate function select GAFR3L_118 1 GPIO 118 alternate function select GAFR3L_119 0 GPIO 119 alternate function select GAFR3L_120 0 GPIO 120 alternate function select Interrupt Controller Mask Register (4-22) ICMR 0x07970f18 00000111 10010111 00001111 00011000 ICMR_IM7 0 Pending IRQ 7 (HWUART) unmasked? ICMR_IM8 1 Pending IRQ 8 (GPIO0) unmasked ICMR_IM9 1 Pending IRQ 9 (GPIO1) unmasked ICMR_IM10 1 Pending IRQ 10 (GPIO2_80) unmasked ICMR_IM11 1 Pending IRQ 11 (USB) unmasked ICMR_IM12 0 Pending IRQ 12 (PMU) unmasked ICMR_IM13 0 Pending IRQ 13 (I2S) unmasked ICMR_IM14 0 Pending IRQ 14 (AC97) unmasked ICMR_IM17 1 Pending IRQ 17 (LCD) unmasked ICMR_IM18 1 Pending IRQ 18 (I2C) unmasked ICMR_IM19 0 Pending IRQ 19 (ICP) unmasked ICMR_IM20 1 Pending IRQ 20 (STUART) unmasked ICMR_IM21 0 Pending IRQ 21 (BTUART) unmasked ICMR_IM22 0 Pending IRQ 22 (FFUART) unmasked ICMR_IM23 1 Pending IRQ 23 (MMC) unmasked ICMR_IM24 1 Pending IRQ 24 (SSP) unmasked ICMR_IM25 1 Pending IRQ 25 (DMA) unmasked ICMR_IM26 1 Pending IRQ 26 (OSMR0) unmasked ICMR_IM27 0 Pending IRQ 27 (OSMR1) unmasked ICMR_IM28 0 Pending IRQ 28 (OSMR2) unmasked ICMR_IM29 0 Pending IRQ 29 (OSMR3) unmasked ICMR_IM30 0 Pending IRQ 30 (RTCCLK) unmasked ICMR_IM31 0 Pending IRQ 31 (RTCALM) unmasked Interrupt Controller Level Register (4-23) ICLR 0x00000000 00000000 00000000 00000000 00000000 ICLR_IL7 0 IRQ 8 (HWUART) generates FIQ? ICLR_IL8 0 IRQ 8 (GPIO0) generates FIQ ICLR_IL9 0 IRQ 9 (GPIO1) generates FIQ ICLR_IL10 0 IRQ 10 (GPIO2_80) generates FIQ ICLR_IL11 0 IRQ 11 (USB) generates FIQ ICLR_IL12 0 IRQ 12 (PMU) generates FIQ ICLR_IL13 0 IRQ 13 (I2S) generates FIQ ICLR_IL14 0 IRQ 14 (AC97) generates FIQ ICLR_IL17 0 IRQ 17 (LCD) generates FIQ ICLR_IL18 0 IRQ 18 (I2C) generates FIQ ICLR_IL19 0 IRQ 19 (ICP) generates FIQ ICLR_IL20 0 IRQ 10 (STUART) generates FIQ ICLR_IL21 0 IRQ 21 (BTUART) generates FIQ ICLR_IL22 0 IRQ 22 (FFUART) generates FIQ ICLR_IL23 0 IRQ 23 (MMC) generates FIQ ICLR_IL24 0 IRQ 24 (SSP) generates FIQ ICLR_IL25 0 IRQ 25 (DMA) generates FIQ ICLR_IL26 0 IRQ 26 (OSMR0) generates FIQ ICLR_IL27 0 IRQ 27 (OSMR1) generates FIQ ICLR_IL28 0 IRQ 28 (OSMR2) generates FIQ ICLR_IL29 0 IRQ 29 (OSMR3) generates FIQ ICLR_IL30 0 IRQ 30 (RTCCLK) generates FIQ ICLR_IL31 0 IRQ 31 (RTCALM) generates FIQ Interrupt Controller Control Register (4-23) ICCR 0x00000001 00000000 00000000 00000000 00000001 ICCR_DIM 0 ONLY enabled and unmasked IRQ bring CPU from idle to run Interrupt Controller IRQ Pending Register (4-24) ICIP 0x00000000 00000000 00000000 00000000 00000000 Interrupt Controller FIQ Pending Register (4-24) ICFP 0x00000000 00000000 00000000 00000000 00000000 Interrupt Controller Pending Register (4-25) ICPR 0x00000000 00000000 00000000 00000000 00000000 ICPR_IS7 0 IRQ 7 (HWUART) pending ICPR_IS8 0 IRQ 8 (GPIO0) pending ICPR_IS9 0 IRQ 9 (GPIO1) pending ICPR_IS10 0 IRQ 10 (GPIO2_80) pending ICPR_IS11 0 IRQ 11 (USB) pending ICPR_IS12 0 IRQ 12 (PMU) pending ICPR_IS13 0 IRQ 13 (I2S) pending ICPR_IS14 0 IRQ 14 (AC97) pending ICPR_IS17 0 IRQ 17 (LCD) pending ICPR_IS18 0 IRQ 18 (I2C) pending ICPR_IS19 0 IRQ 19 (ICP) pending ICPR_IS20 0 IRQ 10 (STUART) pending ICPR_IS21 0 IRQ 21 (BTUART) pending ICPR_IS22 0 IRQ 22 (FFUART) pending ICPR_IS23 0 IRQ 23 (MMC) pending ICPR_IS24 0 IRQ 24 (SSP) pending ICPR_IS25 0 IRQ 25 (DMA) pending ICPR_IS26 0 IRQ 26 (OSMR0) pending ICPR_IS27 0 IRQ 27 (OSMR1) pending ICPR_IS28 0 IRQ 28 (OSMR2) pending ICPR_IS29 0 IRQ 29 (OSMR3) pending ICPR_IS30 0 IRQ 30 (RTCCLK) pending ICPR_IS31 0 IRQ 31 (RTCALM) pending RTC Trim Register (4-30) RTTR 0x00007fff 00000000 00000000 01111111 11111111 RTTR_CK_DIV 7fff RTC Clock Divider Count RTTR_DEL 0 RTC Trim delete Count RTTR_LCK 0 RTC Locking for RTTR RTC Alarm Register (4-30) RTAR 0x001e0d72 00000000 00011110 00001101 01110010 RTC Counter Register (4-31) RCNR 0x00000c9e 00000000 00000000 00001100 10011110 RTC Status Register (4-32) RTSR 0x00000000 00000000 00000000 00000000 00000000 RTSR_AL 0 RTC Alarm Interrupt detected RTSR_HZ 0 RTC Hz Interrupt detected RTSR_ALE 0 RTC Alarm Interrupt Enable RTSR_HZE 0 RTC Hz Interrupt Enable RTSR_RDAL1 0 RTC Wristwatch Alarm 1 Status RTSR_RDALE1 0 RTC Wristwatch Alarm Enable for Writstwatch Alarm 1 RTSR_RDAL2 0 RTC Wristwatch Alarm 2 Status RTSR_RDALE2 0 RTC Wristwatch Alarm Enable for Writstwatch Alarm 2 RTSR_SWAL1 0 RTC Stopwatch Alarm 1 Status RTSR_SWALE1 0 RTC Stopwatch Alarm Enable for Stopwatch Alarm 1 RTSR_SWAL2 0 RTC Stopwatch Alarm 2 Status RTSR_SWALE2 0 RTC Stopwatch Alarm Enable for Stopwatch Alarm 2 RTSR_SWCE 0 RTC Stopwatch Count Enable for SWCR Count Register RTSR_PIAL 0 RTC Periodic Interrupt Alarm Status RTSR_PIALE 0 RTC Periodic Interrupt Alarm Enable RTSR_PICE 0 RTC Periodic Interrupt Count Enable for RTCPICR Count Register Stopwatch alarm register 1 SWAR1 0x00000000 00000000 00000000 00000000 00000000 Stopwatch alarm register 2 SWAR2 0x00000000 00000000 00000000 00000000 00000000 OS Timer Match Register 0 (4-36) OSMR0 0x769ca066 01110110 10011100 10100000 01100110 OS Timer Match Register 1 (4-36) OSMR1 0x00000000 00000000 00000000 00000000 00000000 OS Timer Match Register 2 (4-36) OSMR2 0x00000000 00000000 00000000 00000000 00000000 OS Timer Match Register 3 (4-36) OSMR3 0x00000000 00000000 00000000 00000000 00000000 OS Timer Interrupt Enable Register (4-36) OIER 0x00000001 00000000 00000000 00000000 00000001 OIER_E0 1 OS Interrupt for OSMR0 enabled OIER_E1 0 OS Interrupt for OSMR1 enabled OIER_E2 0 OS Interrupt for OSMR2 enabled OIER_E3 0 OS Interrupt for OSMR3 enabled OS Timer Watchdog Match Enable Register (4-37) OWER 0x00000000 00000000 00000000 00000000 00000000 OWER_WME 0 OSMR3 match causes a reset OS Timer Count Register (4-37) OSCR 0x769c64fa 01110110 10011100 01100100 11111010 OS Timer Status Register (4-38) OSSR 0x00000000 00000000 00000000 00000000 00000000 OSSR_M0 0 OS OSMR0 matched OSCR0 OSSR_M1 0 OS OSMR1 matched OSCR1 OSSR_M2 0 OS OSMR2 matched OSCR2 OSSR_M3 0 OS OSMR3 matched OSCR3 PWM Control Register 0 (4-41) PWMCTL0 0x00000000 00000000 00000000 00000000 00000000 PWMCTL0_PRESCALE 0 PWM0 Prescale Divisor PWMCTL0_SD 0 PWM0 abrupt shutdown PWM Duty Cycle Register 0 (4-42) PWMDUTY0 0x00000000 00000000 00000000 00000000 00000000 PWMDUTY0_DCYCLE 0 PWM0 Duty Cycle PWMDUTY0_FDCYCLE 0 PWM_OUT0 is set high and does not toggle PWM Period Control Register 0 (4-43) PWMPERVAL0 0x00000004 00000000 00000000 00000000 00000100 PWMPERVAL0_PV 4 PWM0 Period Cycle Length PWM Control Register 1 (4-41) PWMCTL1 0x0000000f 00000000 00000000 00000000 00001111 PWMCTL1_PRESCALE 15 PWM1 Prescale Divisor PWMCTL1_SD 0 PWM1 abrupt shutdown PWM Duty Cycle Register 1 (4-42) PWMDUTY1 0x00000200 00000000 00000000 00000010 00000000 PWMDUTY1_DCYCLE 512 PWM1 Duty Cycle PWMDUTY1_FDCYCLE 0 PWM_OUT1 is set high and does not toggle PWM Period Control Register 1 (4-43) PWMPERVAL1 0x000003ff 00000000 00000000 00000011 11111111 PWMPERVAL1_PV 1023 PWM1 Period Cycle Length LCD Controller Control Register 0 (7-23) LCCR0 0x063008f9 00000110 00110000 00001000 11111001 LCCR0_ENB 1 LCD controller enable LCCR0_CMS 0 LCD monochrome operation enable LCCR0_SDS 0 LCD dual panel display enable LCCR0_LDM 1 LCD disable done IRQ disable LCCR0_SFM 1 LCD start of frame IRQ disable LCCR0_IUM 1 LCD fifo underrun error IRQ disable LCCR0_EFM 1 LCD end of frame IRQ disable LCCR0_PAS 1 LCD active display enable LCCR0_DPD 0 LCD send 8 pixel on L_DD[7:0] at each clock LCCR0_DIS 0 LCD controller disable LCCR0_QDM 1 LCD quick disable IRQ disable LCCR0_PDD 0 LCD palette DMA request delay LCCR0_BM 1 LCD branch start IRQ disable LCCR0_OUM 1 LCD fifo underrun IRQ disable LCD Controller Control Register 1 (7-26) LCCR1 0x03070cef 00000011 00000111 00001100 11101111 LCCR1_PPL 239 LCD pixels per line (+1) LCCR1_HSW 3 LCD horizontal sync pulse width (+1) LCCR1_ELW 7 LCD end of line pixel clock wait count (+1) LCCR1_BLW 3 LCD beginning of line pixel clock wait count (+1) LCD Controller Control Register 2 (7-28) LCCR2 0x04080d3f 00000100 00001000 00001101 00111111 LCCR2_LPP 319 LCD lines per panel (+1) LCCR2_VSW 3 LCD vertical sync pulse width (+1) LCCR2_EFW 8 LCD end of frame line clock wait count (+1) LCCR2_BFW 4 LCD beginning of frame line clock wait count (+1) LCD Controller Control Register 3 (7-31) LCCR3 0x04b00009 00000100 10110000 00000000 00001001 LCCR3_PCD 9 LCD pixel clock divisor (+1) LCCR3_ACB 0 LCD AC bias pin frequency (+1) LCCR3_API 0 LCD AC bias pin transitions per interrupt LCCR3_VSP 1 LCD L_FCLK vertical sync polarity active low LCCR3_HSP 1 LCD L_LCLK horizontal sync polarity active low LCCR3_PCP 0 LCD data sampled on falling edge of L_PCLK LCCR3_OEP 1 LCD L_BIAS output enable active low LCCR3_BPP 16 LCD bits per pixel LCCR3_DPC 0 LCD double pixel clock rate at L_PCLK FBR0 FBR0 0xa1979cd0 10100001 10010111 10011100 11010000 LCD Controller Status Register (7-40) LCSR 0x00000010 00000000 00000000 00000000 00010000 LCD Controller Interrupt ID Register (7-41) LIIDR 0x074880ba 00000111 01001000 10000000 10111010 TMED RBG Seed Register (7-42) TRGBBR 0x00aa5500 00000000 10101010 01010101 00000000 TRGBBR_TRS 0 Red Seed TRGBBR_TGS 55 Green Seed TRGBBR_TBS aa Blue Seed TMED Control Register (7-44) TCR 0x0000754f 00000000 00000000 01110101 01001111 TCR_COAM 1 Color Offset Adjuster Matrix TCR_FNAM 1 Frame Number Adjuster Matrix TCR_COAE 1 Color Offset Adjuster Enable TCR_FNAME 1 Frame Number Adjuster Enable TCR_TVBS 4 Vertical Beat Suppression TCR_THBS 5 Horizontal Beat Suppression TCR_TED 1 Energy Distribution Matrix Select FDADR0 FDADR0 0xa1979cd0 10100001 10010111 10011100 11010000 FSADR0 FSADR0 0xa1986780 10100001 10011000 01100111 10000000 FODR0 FIDR0 0x00000000 00000000 00000000 00000000 00000000 LDCMD0 LDCMD0 0x0001e580 00000000 00000001 11100101 10000000 FDADR1 FDADR1 0xa10669d0 10100001 00000110 01101001 11010000 FSADR1 FSADR1 0x00000000 00000000 00000000 00000000 00000000 FIDR1 FIDR1 0x00000000 00000000 00000000 00000000 00000000 LDCMD1 LDCMD1 0x00000000 00000000 00000000 00000000 00000000 SDRAM Configuration Register (6-9) MDCNFG 0x08000ba9 00001000 00000000 00001011 10101001 MDCNFG_DE0 1 SDRAM enable for partition 0 MDCNFG_DE1 0 SDRAM enable for partition 1 MDCNFG_DWID0 0 SDRAM data width (0=32, 1=16) MDCNFG_DCAC0 1 Column address bits for partition pair 0/1 MDCNFG_DRAC0 1 Row address bits for partition pair 0/1 MDCNFG_DNB0 1 Banks in partition pair 0/1 (0=2, 1=4) MDCNFG_DTC0 3 Timing Category for partition pair 0/1 MDCNFG_DADDR0 0 Use alternate addressing for partition pair 0/1 MDCNFG_DLATCH0 1 Return data latching scheme for partition pair 0/1 MDCNFG_DSA11110 0 use SA1111 address muxing for partition pair 0/1 MDCNFG_DE2 0 SDRAM enable for partition 2 MDCNFG_DE3 0 SDRAM enable for partition 3 MDCNFG_DWID2 0 SDRAM data width (0=32, 1=16) MDCNFG_DCAC2 0 Column address bits for partition pair 2/3 MDCNFG_DRAC2 0 Row address bits for partition pair 2/3 MDCNFG_DNB2 0 Banks in partition pair 2/3 (0=2, 1=4) MDCNFG_DTC2 0 Timing Category for partition pair 2/3 MDCNFG_DADDR2 0 Use alternate addressing for partition pair 2/3 MDCNFG_DLATCH2 1 Return data latching scheme for partition pair 2/3 MDCNFG_DSA11112 0 use SA1111 address muxing for partition pair 2/3 SDRAM Refresh Configuration Register (6-15) MDREFR 0x201ba064 00100000 00011011 10100000 01100100 MDREFR_DRI 64 SDRAM Refresh intervall, all paritions MDREFR_E0PIN 0 SDRAM Clock Enable Pin 0 Level MDREFR_K0RUN 1 SDRAM Clock Run Pin 0 MDREFR_K0DB2 0 SDRAM Clock Pin 0 Divide/2 MDREFR_E1PIN 1 SDRAM Clock Enable Pin 1 Level MDREFR_K1RUN 1 SDRAM Clock Run Pin 1 MDREFR_K1DB2 1 SDRAM Clock Pin 1 Divide/2 MDREFR_K2RUN 0 SDRAM Clock Run Pin 2 MDREFR_K2DB2 1 SDRAM Clock Pin 2 Divide/2 MDREFR_APD 1 SDRAM Auto Power Down enable MDREFR_SLFRSH 0 SDRAM Self-Refresh MDREFR_K0FREE 0 SDRAM Free Running Control for SDCLK0 MDREFR_K1FREE 0 SDRAM Free Running Control for SDCLK1 MDREFR_K2FREE 0 SDRAM Free Running Control for SDCLK2 Asynchronous Static Memory Control Register 0 (6-45) MSC0 0x2ffc38f8 00101111 11111100 00111000 11111000 MSC0_RT0 0 nCS[0] ROM Type MSC0_RBW0 1 nCS[0] ROM Bus Width (1=16bit) MSC0_RDF0 15 nCS[0] ROM Delay First Access MSC0_RDN0 8 nCS[0] ROM Delay Next Access MSC0_RRR0 3 nCS[0] ROM/SRAM Recovery Time MSC0_RBUFF0 0 nCS[0] Return Buffer Behavior (1=streaming) MSC0_RT1 4 nCS[1] ROM Type MSC0_RBW1 1 nCS[1] ROM Bus Width (1=16bit) MSC0_RDF1 15 nCS[1] ROM Delay First Access MSC0_RDN1 15 nCS[1] ROM Delay Next Access MSC0_RRR1 2 nCS[1] ROM/SRAM Recovery Time MSC0_RBUFF1 0 nCS[1] Return Buffer Behavior (1=streaming) Asynchronous Static Memory Control Register 1 (6-45) MSC1 0x0000ccd1 00000000 00000000 11001100 11010001 MSC1_RT2 1 nCS[2] ROM Type MSC1_RBW2 0 nCS[2] ROM Bus Width (1=16bit) MSC1_RDF2 13 nCS[2] ROM Delay First Access MSC1_RDN2 12 nCS[2] ROM Delay Next Access MSC1_RRR2 4 nCS[2] ROM/SRAM Recovery Time MSC1_RBUFF2 1 nCS[2] Return Buffer Behavior (1=streaming) MSC1_RT3 0 nCS[3] ROM Type MSC1_RBW3 0 nCS[3] ROM Bus Width (1=16bit) MSC1_RDF3 0 nCS[3] ROM Delay First Access MSC1_RDN3 0 nCS[3] ROM Delay Next Access MSC1_RRR3 0 nCS[3] ROM/SRAM Recovery Time MSC1_RBUFF3 0 nCS[3] Return Buffer Behavior (1=streaming) Asynchronous Static Memory Control Register 2 (6-45) MSC2 0x0000b884 00000000 00000000 10111000 10000100 MSC2_RT4 4 nCS[4] ROM Type MSC2_RBW4 0 nCS[4] ROM Bus Width (1=16bit) MSC2_RDF4 8 nCS[4] ROM Delay First Access MSC2_RDN4 8 nCS[4] ROM Delay Next Access MSC2_RRR4 3 nCS[4] ROM/SRAM Recovery Time MSC2_RBUFF4 1 nCS[4] Return Buffer Behavior (1=streaming) MSC2_RT5 0 nCS[5] ROM Type MSC2_RBW5 0 nCS[5] ROM Bus Width (1=16bit) MSC2_RDF5 0 nCS[5] ROM Delay First Access MSC2_RDN5 0 nCS[5] ROM Delay Next Access MSC2_RRR5 0 nCS[5] ROM/SRAM Recovery Time MSC2_RBUFF5 0 nCS[5] Return Buffer Behavior (1=streaming) Expansion Memory Configuration Register (6-61) MECR 0x00000001 00000000 00000000 00000000 00000001 MECR_NOS 1 Number of Sockets (1=2 Sockets) MECR_CIT 0 Card inserted Synchronous Static Memory Configuration Register (6-33) SXCNFG 0x40044004 01000000 00000100 01000000 00000100 SXCNFG_SXEN0 0 Partition 0 enabled as SX memory SXCNFG_SXEN1 0 Partition 1 enabled as SX memory SXCNFG_SXCL0 1 Partition 0/1 CAS Latency SXCNFG_SXRL0 0 Partition 0/1 RAS Latency SXCNFG_SXRA0 0 Partition 0/1 row address bit count SXCNFG_SXCA0 0 Partition 0/1 column address bit count SXCNFG_SXTP0 0 Partition 0/1 memory type SXCNFG_SXLATCH0 1 Partition 0/1 return data with return clock SXCNFG_SXEN2 0 Partition 2 enabled as SX memory SXCNFG_SXEN3 0 Partition 3 enabled as SX memory SXCNFG_SXCL2 1 Partition 2/3 CAS Latency SXCNFG_SXRL2 0 Partition 2/3 RAS Latency SXCNFG_SXRA2 0 Partition 2/3 row address bit count SXCNFG_SXCA2 0 Partition 2/3 column address bit count SXCNFG_SXTP2 0 Partition 2/3 memory type SXCNFG_SXLATCH2 1 Partition 2/3 return data with return clock MRS value to be written to SX Memory (6-38) SXMRS 0x00000000 00000000 00000000 00000000 00000000 MEM Control for PCMCIA Socket 0 (6-58) MCMEM0 0x00014307 00000000 00000001 01000011 00000111 MCMEM0_SET 7 Address set time MCMEM0_ASST 6 Command assertion time MCMEM0_HOLD 5 Address hold time MEM Control for PCMCIA Socket 1 (6-58) MCMEM1 0x00014307 00000000 00000001 01000011 00000111 MCMEM1_SET 7 Address set time MCMEM1_ASST 6 Command assertion time MCMEM1_HOLD 5 Address hold time ATT Control for PCMCIA Socket 0 (6-59) MCATT0 0x0001c787 00000000 00000001 11000111 10000111 MCATT0_SET 7 Address set time MCATT0_ASST 15 Command assertion time MCATT0_HOLD 7 Address hold time ATT Control for PCMCIA Socket 1 (6-59) MCATT1 0x0001c787 00000000 00000001 11000111 10000111 MCATT1_SET 7 Address set time MCATT1_ASST 15 Command assertion time MCATT1_HOLD 7 Address hold time I/O Control for PCMCIA Socket 0 (6-59) MCIO0 0x0001430f 00000000 00000001 01000011 00001111 MCIO0_SET 15 Address set time MCIO0_ASST 6 Command assertion time MCIO0_HOLD 5 Address hold time I/O Control for PCMCIA Socket 1 (6-59) MCIO1 0x0001430f 00000000 00000001 01000011 00001111 MCIO1_SET 15 Address set time MCIO1_ASST 6 Command assertion time MCIO1_HOLD 5 Address hold time SDRAM Mode Register Set Configuration Register (6-12) MDMRS 0x00320032 00000000 00110010 00000000 00110010 MDMRS_MDBL0 2 SDRAM Partition 0/1 burst length MDMRS_MDADD0 0 SDRAM Partition 0/1 burst type MDMRS_MDCL0 3 SDRAM Partition 0/1 CAS latency MDMRS_MDMRS0 0 MRS value to be written to SDRAM Partition 0/1 MDMRS_MDBL2 2 SDRAM Partition 2/3 burst length MDMRS_MDADD2 0 SDRAM Partition 2/3 burst type MDMRS_MDCL2 3 SDRAM Partition 2/3 CAS latency MDMRS_MDMRS2 0 MRS value to be written to SDRAM Partition 2/3 Boot Time Defaults (6-73) BOOTDEF 0x00000009 00000000 00000000 00000000 00001001 BOOTDEF_BOOTSEL 1 Boot Configuration at BOOT_SEL pins BOOTDEF_PKGTYPE 1 Processor type, 1 for PXA250 Low-Power SDRAM Mode Register Set Configuration Register (6-14) MDMRSLP 0x00000000 00000000 00000000 00000000 00000000 MMC Start/Stop Clock (15-23) MMC_STRPCL 0x00000000 00000000 00000000 00000000 00000000 MMC Status Register (15-24) MMC_STAT 0x00003940 00000000 00000000 00111001 01000000 MMC_STAT_READ_TIME_OUT 0 Read Time Out MMC_STAT_TIME_OUT_RESP 0 Time Out Response MMC_STAT_CRC_WRITE_ERROR 0 CRC Write Error MMC_STAT_CRC_READ_ERR 0 CRC Read Error MMC_STAT_SPI_READ_ERR_TKN 0 SPI Read Error Token MMC_STAT_RES_CRC_ERR 0 Response CRC Error MMC_STAT_XMIT_FIFO_EMPTY 1 Transmit FIFO Empty MMC_STAT_RECV_FIFO_EMPTY 0 Receive FIFO Empty MMC_STAT_CLK_EN 1 Clock Enabled MMC_STAT_DATA_TRAN_DONE 1 Data Transmission Done MMC_STAT_PRG_DONE 1 Program Done MMC_STAT_END_CMD_RES 1 End Command Response MMC Clock Read Timeout Register (15-26) MMC_CLKRT 0x00000000 00000000 00000000 00000000 00000000 MMC_CLK_RATE 0 Read Time Out bitmask MMC SPI mode (15-27) MMC_SPI 0x00000000 00000000 00000000 00000000 00000000 MMC_SPI_EN 0 SPI mode enabled MMC_SPI_CRC_ON 0 CRC generation enabled MMC_SPI_CS_EN 0 SPI chip select enabled MMC_SPI_CS_ADDRESS 0 CS0 enabled MMC Command Data (15-28) MMC_CMDAT 0x00000921 00000000 00000000 00001001 00100001 MMC_CMDAT_RF 1 response format MMC_CMDAT_DATA_EN 0 current cmd includes data transfer MMC_CMDAT_WRITE 0 data transfer is a write MMC_CMDAT_STREAM 0 data transfer is in stream mode MMC_CMDAT_BUSY 1 busy signal is expected after data transfer MMC_CMDAT_INIT 0 precede cmd with 80 clocks MMC_CMDAT_DMA_EN 0 enable DMA mode MMC Response Time Out (15-29) MMC_RESTO 0x00000040 00000000 00000000 00000000 01000000 MMC_RESTO_TO 64 clocks before a response time out MMC Read Time Out (15-29) MMC_RDTO 0x00001dc2 00000000 00000000 00011101 11000010 MMC_RDTO_TO 7618 time until read time out MMC Block Len Register (15-30) MMC_BLKLEN 0x00000200 00000000 00000000 00000010 00000000 MMC_BLKLEN_LEN 512 Number of bytes in the block MMC Block Number Register (15-30) MMC_NOB 0x00000008 00000000 00000000 00000000 00001000 MMC_NOB_N 8 number of blocks MMC Partial Buffer Register (15-31) MMC_PRTBUF 0x00000000 00000000 00000000 00000000 00000000 MMC_PRTBUF_FULL 0 Buffer is partially full MMC Interrupt Mask Register (15-31) MMC_IMASK 0x00001fff 00000000 00000000 00011111 11111111 MMC_IMASK_DATATRAN 1 Data Transfer Done masked MMC_IMASK_PRGDONE 1 Programming Done masked MMC_IMASK_ENDCMD 1 End Command Response masked MMC_IMASK_STOPCMD 1 Ready for Stop Transaction Command masked MMC_IMASK_CLOCKOFF 1 Clock Is Off masked MMC_IMASK_RXFIFO 1 Receive FIFO Read Request masked MMC_IMASK_TXFIFO 1 Transmit FIFO Write Request masked MMC Interrupt Register (15-33) MMC_IREG 0x00000007 00000000 00000000 00000000 00000111 MMC_IREG_DATATRAN 1 Data Transfer Done or Read TimeOut occured MMC_IREG_PRGDONE 1 Card has finished programming MMC_IREG_ENDCMD 1 MMC has received response or Response TimeOut MMC_IREG_STOPCMD 0 MMC is ready for the Stop Transaction Command MMC_IREG_CLOCKOFF 0 MMC clock has been turned off MMC_IREG_RXFIFO 0 Request for data read from receive FIFO MMC_IREG_TXFIFO 0 Request to data write to transmit FIFO MMC Command Register (15-34) MMC_CMD 0x0000004c 00000000 00000000 00000000 01001100 MMC_CMD_INDEX c command index MMC Higher Argument Register (15-36) MMC_ARGH 0x00000000 00000000 00000000 00000000 00000000 MMC_ARGH_ARG 0 upper 16 bits of command argument MMC Lower Argument Register (15-36) MMC_ARGL 0x00000000 00000000 00000000 00000000 00000000 MMC_ARGL_ARG 0 upper 16 bits of command argument